RT1176 DQS pin and SEMC DQS read strobe mode for SDRAM at 166 MHz

[mjosborne1]

Hello,

I have a couple of questions regarding the RT1176 DQS signal and SEMC DQS read strobe mode configuration I was hoping someone could help me with...

I have found several forum posts talking about this issue, and reviewed the reference manual, data sheet and EVK documentation; however, I'm still confused.

On our board the DQS pin is floating (like the EVK, the SDRAM part we're using doesn't support this signal).  We currently configure the DQS pin as follows:

• SW_MUX_CTL_PAD_GPIO_EMC_B1_39
  • 0x0000_0010, (i.e. SION := 1, MUX_MODE := 0)
• SW_PAD_CTL_PAD_GPIO_EMC_B1_39
  • 0x0000_0008, (i.e. DWP_LOCK : = 0, DWP := 0, ODE := 0, PULL := 2, PDRV := 0)

This configuration lines up with guidance from the EVK schematic, the hardware development guide, and the DCD configuration in sample projects:

• 
• 

However, the DCD configuration in sample projects sets:

• SEMC_MCR.DQSMD := 1 (Dummy read strobe loopbacked from DQS pad).

We initially used this setting but noticed that some boards were having occasional SDRAM read errors when running at 166 MHz.  We then changed the SEMC DQS (read strobe) mode MCR.DQSMD := 0 (Dummy read strobe loopbacked internally), and this appeared to resolve the issue (SDRAM still running at 166 MHz).  However, we are finding that at higher temperatures we are again having occasional SDRAM read errors when running at 166 MHz.  The SDRAM manufacturer (ISSI) has reviewed the timing settings we are using and did not find any issues.

This configuration is consistent with the post here:

But seems to contradict information in the reference manual and datasheet:

• 
• 

Some things I'm not sure about:

• Is SEMC MCR.DQSMD := 1 required for 166 MHz operation?
• When the SEMC MCR.DQSMD := 0, does the DQS pin have any affect on SEMC read timing?
• When the SEMC MCR.DQSMD := 0, does the SEMC DCCR have any affect on SEMC read timing?

Or is it not that simple, and maybe:

• It may work at 166 MHz with DQS floating and MCR.DQSMD := 0, but this depends on the h/w layout.
• It will work at 166 MHz with MCR.DQSMD := 1, but DQS needs to be loaded/tuned based on the h/w layout.

Thanks in advance for the help.

[Omar_Anguiano]

Hello
I hope you are well. 

The timing for sampling with an internal dummy read strobe loopback is very similar to the timing for loopback from pad. Sampling with a dummy read strobe loopback from the DQS pad can achieve a higher read frequency.
So for the maximum frequency SEMC MCR.DQSMD = 1 with DQS pad floating; you can add a capacitor to adjust timing.

Best regards,
Omar

[mjosborne1]

Thank you for the response.

Can you please confirm the behaviour of SEMC DCCR.SDRAMVAL and how it relates to SEMC MCR.DQSMD?

i.e. Is it only used by the SEMC when SEMC MCR.DQSMD := 0?

In my testing, different SEMC DCCR.SDRAMVAL values do not appear to have any effect when SEMC MCR.DQSMD := 1.

However, when the "SEMC configuration patch: SDRAM @200 MHz SDRAM patch" is enabled in MCU Config Tools the generated code is also changing the DCCR.SDRAMVAL value:

Also, is there any guidance on how to route the DQS pad and determine the capacitance value when SEMC MCR.DQSMD := 1?

i.e. Does the trace length need to be the same as the data lines?
Is it valid to have this line floating with nothing connected?

Thank you

[Omar_Anguiano · Accepted solution]

DCCR is applicable to both DQSMD(1/0) as it adds a delay to it. The impact will depend on various design factors like PCB trace, pad capacitance, etc.
Unfortunately, there is no formula or guide to choose the adequate capacitance for DQS, you will need to try different capacitances and stay with the one that fits your application.

Yes, it is valid to leave DQS floating or put some cap loads on board level to compensate DATA/CLK pins
load.

Best regards,
Omar