In my board I have an FPGA master from SPI, and the RT1051 is the slave
"Normal" SPI transactions are 279 bytes long, so I programmed the DMA to trigger an interrupt every 279 bytes.
For various causes it may happen that the FPGA may abort the transaction before 279 bytes. RT1051 should notice "aborted/partial" transactions.
I was thinking of using the "Frame Complete Flag" interrupt, which should trigger an interrupt when the PCS is deasserted.
But how can I tell the difference between a competed transaction and an aborted one after it has jumped into the interrupt handler? I would need to know the "true" number of bytes that the SPI received in the last transaction.
Then how do I get/calculate this number? I can't trust the DMA that it might not have transferred the last received SPI byte yet (it might be busy on another channel, or it might be bus busy). I can't use interrupts since there would be too many of them and the risk of losing some bytes by miscounting them is high. It would also be too onerous in terms of processing.
I can't use "Word Output Trigger," which would be perfect via XBAR and a timer counter, but unfortunately on RT105x this trigger is not connected to XBAR (nor any other)
Do you have any other ideas for obtaining/calculating the number of bytes received on SPI?
Or maybe you have a different idea to distinguish a completed transaction from an aborted one?
best regards
Max
