Hello, we have some secure fused RT600 chips which have external SWD debugging disabled through OTP fuses. In particular, the BOOT_CFG, SEC_BOOT_CFG, and DCFG_CC_SOCU fuses:
# BOOT_CFG[0]:
# - enable Secure Boot, bits 20-21
# - skip DICE, bit 23
efuse-program-once 96 00B00000
# SEC_BOOT_CFG[5]:
# - block PUF, bit 8 and 9
efuse-program-once 101 00000300
# DCFG_CC_SOCU:
# - FORCE_UUID_MATCH, bit 24: force per-device unique debug certs
# - CRC8: bits 0-8
efuse-program-once 95 01000052
# DCFG_CC_SOCU_AP: antipole of DCFG_CC_SOCU
efuse-program-once 104 FEFFFFAD
From reading the datasheet my understanding is this could only be enabled through SWD by using a specially provided NXP secure provisioning SDK. I am just wondering from the CM33 side (and if so, how?)
