Optimized ADC configuration for RT1060

[kurt_staubli]

We use MIMXRT1060CVJ45A as a motor controller. I try to optimize ADC parameters used for current sense to increase speed with the same accuracy.

I qualify accuracy by calculate standard deviation of many samples.

The actual parameters are the following:

...
adc_config_t k_adcConfig;                                                                                                                                         
ADC_GetDefaultConfig(&k_adcConfig);                                                                                                                               
k_adcConfig.enableOverWrite = true;                                                                                                                               
k_adcConfig.enableHighSpeed = true;                                                                                                                               
k_adcConfig.enableLongSample = false;                                                                                                                             
k_adcConfig.samplePeriodMode = kADC_SamplePeriodShort4Clocks;                                                                                                     
k_adcConfig.enableAsynchronousClockOutput = false; // Has to be false, see https://community.nxp.com/t5/i-MX-Processors/ADC-SyncMode-Noise/m-p/992934             
k_adcConfig.clockSource = kADC_ClockSourceIPG;                                                                                                                    
k_adcConfig.clockDriver = kADC_ClockDriver4;      
...                                                                                                                                                                                                                                                                                                                                            

When I decrease samplePeriodMode, I decrease accuracy significantly and speed is increased only a bit (since this parameter affects only sampling, not conversion).

When I decrease clockDriver, I increase ADC's clock frequency (FADCK). If I set it to kADC_ClockDriver2, FADCK increases from 33MHz to 66MHz. Speed is improved significantly and accuracy is even a bit better. But NXP limits FADCK to 4...40 MHz for our CPU.

My question:

How does a violation of the limits of FADCK manifest itself?

Are there any other parameters for improving speed without affecting accuracy?

[FelipeGarcia · Accepted solution]

Hi Kurt,

Regarding your questions:

1. Please check this note from the RM:

The ADCK frequency must be between fADCK minimum and fADCK maximum to meet ADC specifications.

This will mean that we will not be able to guarantee ADC measurements and specification if clock is outside recommended range.

2. As you mentioned the limit is 40 MHz so if what you need is to increase FADCK then I am afraid it is not recommended as it could cause unpredicted behavior.

Best regards,

Felipe

[kurt_staubli]

Hi Felipe

I almost expected this answer

So I cannot improve ADC's performance.

Thanks anyway.

Best regards

Kurt