MDC frequency generation issues

[jautry]

In the iMXRT spec, it states that if 50Mhz is used for the reference clock then placing a value of x9 in the MSCR register should provide the 2.5mhz MDC clock to the ethernet phy.  Unfortunately, when I do that, I get a higher frequency around 7mhz.  I measured the ref_clock and it was at 50mhz.  Are there other dividers somewhere which affect this, or do I have some clocking mis-selected.  I have to place a value of around 0x40 in the MSCR register to get the proper frequency.

[jautry]

??? That is what I did per my last entry.  I had to put a value of 0x140 into the MSCR to get to 2.5mhz.

[xiangjun_rong]

Hi,

As the following pic, you can write the

ENET->MSCR&=~(0x3F<<1);

ENET->MSCR|=0x09<<1;

BTW, for your code, in the debugger, pls check the ENET->MSCR register and check if the MII_SPEED bits is 0x09.

Hope it can help you

BR

XiangJun Rong

xiangjun_rong_0-1665307931919.png

[jautry]

Ok if I set MSCR register to 0x112, I get .14us clock or about 7mhz.  The ref_clk is measured at .02us or 50mhz (measured with a scope).  I would expect to get 2.5mhz out.  I have to set MSCR to 0x140 in order to get the 2.5mhz.

[xiangjun_rong]

Hi,

Pls try to use different MII_SPEED value and test the MDC clock frequency until it is 2.5MHz.

BR

XiangJun Rong