IMXRT1064 External SRAM Usage

[Lukas_Frank]

Hi Dear Authorized,

I am looking for some informations related to external SRAM usage with IMXRT1064. For example, EVK has 256Mbit 166MHz SDRAM. 166MHz is related with used SDRAM. I am trying to find frequency limitations of SEMC Controller. Also, looking for SRAM usage.

Question 1 : Is there an upper frequency (like 166MHz, below or above) limitation for SEMC Controller while using external SRAM?

Question 2 : Is there a specific document which describes SRAM usage and implementation in IMXRT by using SEMC Controller?

Question 3 : Could you please share me example code for SRAM usage with SEMC Controller?

Thanks and Regards.

[lucas_cao]

Hi 

I would like to share some infromation to you.

1. The Max frequency of SEMC is 166MHz, you can find it in datasheet.

2. I am not sure for this

3. The demo code, you can find in our SDK code, path : boards\evkbmimxrt1060\driver_examples\semc\sdram

[Lukas_Frank]

Hi Dear @lucas_cao,

Could you please help me about my Question 2 ? I want to you to prepare a document about the issue if possible.

thank and regards.

[Hui_Ma · Accepted solution]

Hi Lukas,

Please refer below knowledge thread about using SEMC module with external SRAM memory device.

https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/How-to-configure-SRAM-in-SEMC-modules-for-RT-dev...

Wish it helps.

Mike

[Lukas_Frank]

Hi Dear @Hui_Ma ,

I tested the code and I stucked at some points. Here is the steps which I follow:

First of all, I directly tried the code which you share with me. It errors due to some enums such as "BOARD_INITPINS_WAIT_CTRL_PERIPHERAL" , "BOARD_INITPINS_WAIT_CTRL_CHANNEL" which belongs to RT1170. So, I simplified the code like below. I tried it like official SDRAM EVK example.

The code is not able to write data to memory address 0x80000000 while I am using SRAM configuration despite it is successfully write SDRAM. The successful tests which are achieved uses SDK example "evkmimxrt1064\driver_examples\semc\sdram". It works well but the code below is not writing data to address.

My card includes both SRAM and SDRAM. I just want to use SEMC for both of them. Could you help me please what is wrong with the below code?

Thanks and Regards.

#include "fsl_debug_console.h"
#include "fsl_device_registers.h"
#include "pin_mux.h"
#include "clock_config.h"
#include "board.h"
#include "fsl_semc.h"

/*******************************************************************************
 * Definitions
 ******************************************************************************/
#define EXAMPLE_SEMC               SEMC
#define EXAMPLE_SEMC_START_ADDRESS (0x80000000U)
#define EXAMPLE_SEMC_CLK_FREQ      CLOCK_GetFreq(kCLOCK_SemcClk)

#define SEMC_EXAMPLE_DATALEN    (0x1000U)
#define SEMC_EXAMPLE_WRITETIMES (1000U)

/*******************************************************************************
 * Prototypes
 ******************************************************************************/
extern status_t BOARD_InitSEMC(void);
static void SEMC_SDRAMReadWrite32Bit(void);
/*******************************************************************************
 * Variables
 ******************************************************************************/

uint32_t sram_writeBuffer[SEMC_EXAMPLE_DATALEN];
uint32_t sram_readBuffer[SEMC_EXAMPLE_DATALEN];

/*******************************************************************************
 * Code
 ******************************************************************************/
void SEMC_SRAMReadWrite32Bit(void);
#define SRAM_BASE EXAMPLE_SEMC_START_ADDRESS //0x90000000
status_t BOARD_InitSRAM(void)
{
    semc_config_t config;
    semc_sram_config_t sram_config;
    uint32_t clockFrq = EXAMPLE_SEMC_CLK_FREQ;

    /* Initializes the MAC configure structure to zero. */
    memset(&config, 0, sizeof(semc_config_t));
    memset(&sram_config, 0, sizeof(semc_sram_config_t));

    /* Initialize SEMC. */
    SEMC_GetDefaultConfig(&config);
    config.dqsMode = kSEMC_Loopbackdqspad; /* For more accurate timing. */
    SEMC_Init(SEMC, &config);

// config SRAM
    sram_config.cePinMux           = kSEMC_MUXA8;        	// SEMC_ADDR08 is CE0# (IOCR[MUX_A8])
    sram_config.address            = SRAM_BASE;          	// Base address 0x90000000 (BR6[BA])
    sram_config.memsize_kbytes     = 0x10000;				// SRAM0 space size 64MB (BR6[MS])
    sram_config.addrPortWidth      = 8;                    	// Port width (SRAMCR0[COL]) Don't care in SRAM.
    sram_config.advActivePolarity  = kSEMC_AdvActiveLow;   	// ADV# polarity (SRAMCR0[ADVP]) Don't care if not use ADV.
    sram_config.addrMode           = kSEMC_AddrDataNonMux; 	// Non Mux mode (SRAMCR0[AM])
    sram_config.burstLen           = kSEMC_Nor_BurstLen1;	// Burst length (SRAMCR0[BL])
    sram_config.portSize           = kSEMC_PortSize16Bit;	// Port size 16bit (SRAMCR0[PS])
    //sram_config.syncMode           = kSEMC_AsyncMode;		// ASYNC mode (SRAMCR0[SYNCEN])
    //sram_config.waitEnable         = true;				// WAIT enable (SRAMCR0[WAITEN])
    //sram_config.waitSample         = 0; 					// WAIT sample (SRAMCR0[WAITSP])
    //sram_config.advLevelCtrl       = kSEMC_AdvHigh; 		// ADV# level control (SRAMCR0[ADVH]) Don't care if not use ADV.
    sram_config.tCeSetup_Ns        = 20; 					// CE# setup time [nsec] (SRAMCR1[CES]) Need tuning.
    sram_config.tCeHold_Ns         = 20;					// CE# hold time [nsec] (SRAMCR1[CEH]) Need tuning.
    sram_config.tCeInterval_Ns     = 20; 					// CE# interval time [nsec] (SRAMCR2[CEITV]) Need tuning.
    //sram_config.readHoldTime_Ns    = 20; 					// Read hold time [nsec] (SRAMCR2[RDH]) Only for SYNC mode.
    sram_config.tAddrSetup_Ns      = 20; 					// ADDR setup time [nsec] (SRAMCR1[AS]) Need tuning.
    sram_config.tAddrHold_Ns       = 20;					// ADDR hold time [nsec] (SRAMCR1[AH]) Need tuning.
    sram_config.tWeLow_Ns          = 20; 					// WE low time [nsec] (SRAMCR1[WEL]) Need tuning.
    sram_config.tWeHigh_Ns         = 20; 					// WE high time [nsec] (SRAMCR1[WEH]) Need tuning.
    sram_config.tReLow_Ns          = 20; 					// RE low time [nsec] (SRAMCR1[REL]) Need tuning.
    sram_config.tReHigh_Ns         = 20;					// RE high time [nsec] (SRAMCR1[REH]) Need tuning.
    sram_config.tTurnAround_Ns     = 20; 					// Turnaround time [nsec] (SRAMCR2[TA]) Need tuning but don't set it to be 0.
    sram_config.tAddr2WriteHold_Ns = 20;					// Address to write data hold time [nsec] (SRAMCR2[AWDH]) Need tuning.
    sram_config.tWriteSetup_Ns     = 20; 					// Write Data setup time [nsec] (SRAMCR2[WDS]) Only for SYNC mode.
    sram_config.tWriteHold_Ns      = 20; 					// Write Data hold time [nsec] (SRAMCR2[WDH]) Only for SYNC mode.
    sram_config.latencyCount       = 20; 					// Latency count [nsec] (SRAMCR2[LC]) Only for SYNC mode.
    sram_config.readCycle          = 20; 					// read time [nsec] (SRAMCR2[RD]) Only for SYNC mode.
    //sram_config.delayChain         = 20; 					// typically not used in SRAM. (DCCR [SRAMXVAL], DCCR [SRAMXEN], DCCR [SRAM0VAL], DCCR [SRAM0EN])

    return SEMC_ConfigureSRAM(SEMC, &sram_config, clockFrq);
}

#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN
#include "fsl_cache.h"
#endif

/*!
 * @brief Main function
 */
int main(void)
{
    /* Hardware initialize. */
    BOARD_ConfigMPU();
    BOARD_InitBootPins();
    BOARD_InitBootClocks();

    CLOCK_InitSysPfd(kCLOCK_Pfd2, 29);
    /* Set semc clock to 163.86 MHz */
    CLOCK_SetMux(kCLOCK_SemcMux, 1);
    CLOCK_SetDiv(kCLOCK_SemcDiv, 1);
    BOARD_InitDebugConsole();

    if (BOARD_InitSRAM() != kStatus_Success)
    {
        PRINTF("\r\n SEMC SRAM Init Failed\r\n");
    }

    SEMC_SRAMReadWrite32Bit();

}

void SEMC_SRAMReadWrite32Bit(void)
{
    uint32_t index;
    uint32_t datalen = SEMC_EXAMPLE_DATALEN;
    uint32_t *sram  = (uint32_t *)EXAMPLE_SEMC_START_ADDRESS; /* SDRAM start address. */
    bool result      = true;

    PRINTF("\r\n SEMC SDRAM Memory 32 bit Write Start, Start Address 0x%x, Data Length %d !\r\n", sram, datalen);
    /* Prepare data and write to SDRAM. */
    for (index = 0; index < datalen; index++)
    {
        sram_writeBuffer[index] = index;
        sram[index]             = sram_writeBuffer[index];
    }

    PRINTF("\r\n SEMC SDRAM Read 32 bit Data Start, Start Address 0x%x, Data Length %d !\r\n", sram, datalen);

#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN
    DCACHE_InvalidateByRange(EXAMPLE_SEMC_START_ADDRESS, 4U * SEMC_EXAMPLE_DATALEN);
#endif

    for (index = 0; index < datalen; index++)
    {
    	sram_readBuffer[index] = sram[index];
    }

    PRINTF("\r\n SEMC SDRAM 32 bit Data Write and Read Compare Start!\r\n");
    /* Compare the two buffers. */
    while (datalen--)
    {
        if (sram_writeBuffer[datalen] != sram_readBuffer[datalen])
        {
            result = false;
            break;
        }
    }

    if (!result)
    {
        PRINTF("\r\n SEMC SRAM 32 bit Data Write and Read Compare Failed!\r\n");
    }
    else
    {
        PRINTF("\r\n SEMC SRAM 32 bit Data Write and Read Compare Succeed!\r\n");
    }
}

[Hui_Ma]

Hi,

Please make sure external SRAM base address is different with SDRAM setting (SEMC BR0 register BA value different with SEMC BR6 BA value).

Could you please provide the SRAM device related schematics for double check?

best regards,

Mike

[Lukas_Frank]

Hi Dear @Hui_Ma ,

First of all, I have a long answer and thank you for your patience. I really need SRAM usage for my  startup's mass production.

I set SRAM base address as 0x80000000. You are right. I will share the schematics when my colleague forward it. 

I find two problem related to my issue.

• First is in my Board_Init during setting clock configurations. I am setting pinmux as below line for clock:

IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_26_SEMC_CLK, 0U);

But I should use SEMC_CLKX0 or CLKX1 according to Table 25-6 in Reference Manual (RT1064). 

• Question 1: According to this table I will fail when I use "IOMUXC_GPIO_EMC_26_SEMC_CLK". Is that true?

• Second problem is in my card. I am using GPIO_EMC_26 pin for SRAM CLK.

• Question 2 : Which physical pin should I use for RT1064 is there an alternative for SEMC_CLK (GPIO_EMC26). I can't find SEMC_CLKX0 (Not Found in RM) and SEMC_CLKX1 (Not Found in RM) ? There is physical pins for RT1170 SRAM Usage in below figure for the clocks sequentially GPIO_EMC_B2_19 and GPIO_EMC_B2_20. But there is no physical pins for RT1064. I compare my Board_Init and the officials example's (RT1170 SRAM Example) Board_Init, I have also attached them.

• Question 3: 

Could you please help me about the second parameter for IOMUXC_SetPinConfig method ? In the official RT1170 example second parameter is set as "0x08U" but I don't know where to look it for RT1064. Below is what I mention in this question.

IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_26_SEMC_CLK, 0U);
//IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_02_SEMC_CLK5, 0U);
//IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_SEMC_CLK5, this is set "0x08U" for 1170. what should I set it for 1064);

As a summary I don't both have reference value for  and also example for RT1064. How can I use SRAM in these conditions? 

Thanks and Regards.

[Hui_Ma]

Hi Lukas,

You are right. When SEMC connects with external SRAM device, it needs to use SEMC_CLKX0 or SEMC_CLKX1.
There with below note about SEMC_CLKX0 or SEMC_CLKX1 related pad:

SEMC_CLK5 related PAD is  GPIO_EMC_40 or GPIO_SD_B0_02 with MUX_MODE ALT9:

or 

SEMC_CLK6 related pad is GPIO_AD_B0_11 or GPIO_SD_B0_03, both MUX_MODE is ALT9

Just use SEMC_CLKX0 as an example, related code would be:

IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_SEMC_CLK5, 0U);

The last parameter Software input on field, which default valie is 0x0.

More detailed info, please refer IOMUXC_SetPinMux() funtion in <fsl_iomuxc.h> file.

Wish it helps.

Mike

[Lukas_Frank]

Hi Dear @Hui_Ma ,

My Question 1:

Actually, I look IOMUXC_SetPinMux function for details. But, there is no reference values for any specific functionality even if the default values are 0x0. For example, why below line uses "0x110F9U" ? Can I use 0x0 for everything which will I newly configure?

IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_40_SEMC_RDY, 0x0110F9U); 

My Question 2:

I have additional blurry points for configuring my SRAM. You said about related PADs for SEMC_CLK5 and SEMC_CLK6 in your answer. (SEMC_CLKX0 and SEMC_CLKX1). I can't use SYNC mode due to some bugs in code. There is no definition for SEMC_SRAMCR4_SYNCEN_MASK in code. This is why I can't use SYNC Mode. And it is not fixed when I configure by "Config Tool". When I select SYNC mode option "Config Tool" is not recommending any code change related about it. Is this not the real purpose of "Config Tool" ? I find the corresponding definitions 

For IMXRT1170:

#define SEMC_SRAMCR4_SYNCEN_MASK                 (0x2U)
#define SEMC_SRAMCR4_SYNCEN_SHIFT                (1U)
/*! SYNCEN - Select SRAM controller mode.
 *  0b0..ASYNC mode is enabled.
 *  0b1..SYNC mode is enabled.
 */
#define SEMC_SRAMCR4_SYNCEN(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_SYNCEN_SHIFT)) & SEMC_SRAMCR4_SYNCEN_MASK)

For IMXRT1064:

#define SEMC_SRAMCR0_SYNCEN_MASK                 (0x2U)
#define SEMC_SRAMCR0_SYNCEN_SHIFT                (1U)
/*! SYNCEN - Synchronous Mode Enable
 *  0b0..Asynchronous mode is enabled.
 *  0b1..Synchronous mode is enabled. Only fixed latency mode is supported.
 */
#define SEMC_SRAMCR0_SYNCEN(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_SYNCEN_SHIFT)) & SEMC_SRAMCR0_SYNCEN_MASK)

And there are too many points which requires change (*prefix*_SRAMCR4_*postfix* to *prefix*_SRAMCR0_*postfix* ) to use SYNC mode. Why these definition based differences is not suitable for IMXRT1064 and why they are not configuring by Config Tools when I set SYNC Mode option? 

fsl_semc.c  (Original for IMXRT1064) :

        else
#endif /* FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT */
        {
            tempCtrlVal = SEMC_SRAMCR0_PS(config->portSize) |
#if defined(SEMC_SRAMCR4_SYNCEN_MASK) && (SEMC_SRAMCR4_SYNCEN_MASK)
                          SEMC_SRAMCR0_SYNCEN(config->syncMode) |
#endif /* SEMC_SRAMCR4_SYNCEN_MASK */
                          SEMC_SRAMCR0_BL(config->burstLen) | SEMC_SRAMCR0_AM(config->addrMode) |
                          SEMC_SRAMCR0_ADVP(config->advActivePolarity) |
#if defined(SEMC_SRAMCR4_ADVH_MASK) && (SEMC_SRAMCR4_ADVH_MASK)
                          SEMC_SRAMCR4_ADVH(config->advLevelCtrl) |
#endif /* SEMC_SRAMCR4_ADVH_MASK */
                          SEMC_SRAMCR0_COL_MASK;
        }

fsl_semc.c  (Configured by me for IMXRT1064) :

        else
#endif /* FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT */
        {
            tempCtrlVal = SEMC_SRAMCR0_PS(config->portSize) |
//#if defined(SEMC_SRAMCR4_SYNCEN_MASK) && (SEMC_SRAMCR4_SYNCEN_MASK)
#if defined(SEMC_SRAMCR0_SYNCEN_MASK) && (SEMC_SRAMCR0_SYNCEN_MASK)
                          SEMC_SRAMCR0_SYNCEN(config->syncMode) |
#endif /* SEMC_SRAMCR0_SYNCEN_MASK */
//#endif /* SEMC_SRAMCR4_SYNCEN_MASK */
                          SEMC_SRAMCR0_BL(config->burstLen) | SEMC_SRAMCR0_AM(config->addrMode) |
                          SEMC_SRAMCR0_ADVP(config->advActivePolarity) |
#if defined(SEMC_SRAMCR4_ADVH_MASK) && (SEMC_SRAMCR4_ADVH_MASK)
                          SEMC_SRAMCR4_ADVH(config->advLevelCtrl) |
#endif /* SEMC_SRAMCR4_ADVH_MASK */
                          SEMC_SRAMCR0_COL_MASK;
        }

I just want to ask you: What is the reason this bug is exist even I have "fsl_semc.c" which is belong to IMXRT1064 SDK. 

I am asking detailly because I don't want to fluctuate in configuration phase.

Thanks and Regards.

[Hui_Ma]

Hi, Lukas,

Answer your Q1:

There are two different SetPin functions with below definition: IOMUXC_SetPinMux() & IOMUXC_SetPinConfig()

/*!
 * @brief Sets the IOMUXC pin mux mode.
 * @note The first five parameters can be filled with the pin function ID macros.
 *
 * This is an example to set the PTA6 as the lpuart0_tx:
 * @code
 * IOMUXC_SetPinMux(IOMUXC_PTA6_LPUART0_TX, 0);
 * @endcode
 *
 * This is an example to set the PTA0 as GPIOA0:
 * @code
 * IOMUXC_SetPinMux(IOMUXC_PTA0_GPIOA0, 0);
 * @endcode
 *
 * @Param muxRegister  The pin mux register.
 * @Param muxMode      The pin mux mode.
 * @Param inputRegister The select input register.
 * @Param inputDaisy   The input daisy.
 * @Param configRegister  The config register.
 * @Param inputOnfield   Software input on field.
 */
static inline void IOMUXC_SetPinMux(uint32_t muxRegister,
                                    uint32_t muxMode,
                                    uint32_t inputRegister,
                                    uint32_t inputDaisy,
                                    uint32_t configRegister,
                                    uint32_t inputOnfield)
{
    *((volatile uint32_t *)muxRegister) =
        IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);

    if (inputRegister != 0UL)
    {
        *((volatile uint32_t *)inputRegister) = inputDaisy;
    }
}

&

/*!
 * @brief Sets the IOMUXC pin configuration.
 * @note The previous five parameters can be filled with the pin function ID macros.
 *
 * This is an example to set pin configuration for IOMUXC_PTA3_LPI2C0_SCLS:
 * @code
 * IOMUXC_SetPinConfig(IOMUXC_PTA3_LPI2C0_SCLS,IOMUXC_SW_PAD_CTL_PAD_PUS_MASK|IOMUXC_SW_PAD_CTL_PAD_PUS(2U))
 * @endcode
 *
 * @Param muxRegister  The pin mux register.
 * @Param muxMode      The pin mux mode.
 * @Param inputRegister The select input register.
 * @Param inputDaisy   The input daisy.
 * @Param configRegister  The config register.
 * @Param configValue   The pin config value.
 */
static inline void IOMUXC_SetPinConfig(uint32_t muxRegister,
                                       uint32_t muxMode,
                                       uint32_t inputRegister,
                                       uint32_t inputDaisy,
                                       uint32_t configRegister,
                                       uint32_t configValue)
{
    if (configRegister != 0UL)
    {
        *((volatile uint32_t *)configRegister) = configValue;
    }
}

Answer your question 2:

Sorry for our SDK software code error, the SYNCEN bit was located at SRAMCR0 register.

I will report this issue and our software team will fix it at new released MCUXpresso SDK code.

Sorry again for that may bring any inconvenience to you.

best regards,

Mike

[Lukas_Frank]

Hi Dear @Hui_Ma ,

For the Question 1:

You are right, there are two function. But I just want to ask again about my curiousity related to the reference values. Why below line uses "0x110F9U" ? What is the meaning of value "0x110F9U" ? How can I achieve this type of reference values while using "SetPinConfig" function. What are the reference values for each pin's MuxMode ? Will it require set it manually each time?

For the Question 2:

Can I configure SYNC mode by manually until new SDK released? 

Thanks and Regards.

[Hui_Ma]

Hi Lukas,

1> Why below line uses "0x110F9U" ? What is the meaning of value "0x110F9U" ? 

TS: Related value was loaded into related pad control register, For example: Address 0x401F_8250 IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19

This register will set Pad Pull-up/down, Hysteresis, Open Drain, Speed, Driver Strength and Slew rate.

Related register bit info could be found at RT1064 reference manual chapter 11.6.144.

About why need to set pad config value with "0x110F9U",  that was based on pad digital function.

Customer also can use MCUXpresso Configuration Tools (Pins) to batch handle pads control configuration.

In general, please use NXP SDK demo provided pad cofiguration as a reference.

2> The SDK software bug was reported, while there still take time for software team to handle and fix at new released SDK software. The interval could be a few months. I think customer can continue project design without waiting for new version SDK released. Thank you for the understanding.

Best regards,

Mike

[Lukas_Frank]

Hi Dear @Hui_Ma ,

Thank you for all your helps. I just want to add something related to SDK Update. I have figure out more about errors in "fsl_semc.c" file.

WAITEN and RDH register regions have similar issues in the code as we can see below pictures. WAITEN has no register set property in IMXRT1064 but it required definition in the code -->[1]. In addition, RDH is required configuration for SYNC mode usage but it is connected to "fsl_semc.c" by SEMC_SRAMCR6_RDH although it is the register element of CR2 -->[2]. Also, I don't know whether I should enable or not enable FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME -->[3]. It can be more missing point which I can't realized now.

Has IMXRT1064 RDH feature for SEMC?

Thanks and Regards.

-------------------------------[1]-------------------------------

-------------------------------[2]-------------------------------

-------------------------------[3]-------------------------------

[Hui_Ma]

Hi Lukas,

First of all, sorry for the later reply.

RT1064 SEMC module registers do not have WAITEN bit, which was belongs to eFlexPWM modules.
<fsl_semc.c> driver file was a general SEMC moudle driver code, which was definied to suitable for SEMC module IP with different versions.

About SEMC module SRAM Control Register 2 (SRAMCR2) [RDH] bit and <MIMXRT1064_features.h> file below marcro definition, I will check with RT product team for double confirm. I will let you know when there with any feedback:

/* @brief Has read hold time feature (register bit field SRAMCR6[RDH]). */
#define FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME (0)

best regards,

Mike

[Lukas_Frank]

Hi Dear @Hui_Ma ,

I am appreciate for your help. I will try it on my board and share my results.

Best wishes.