Flex Spi Serial Clk not running at the requested speed 100MHz after ROM configuration of the CCM

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Flex Spi Serial Clk not running at the requested speed 100MHz after ROM configuration of the CCM

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Maximvda
Contributor III

Hi,

We are working on a project using the MCU Expresso VSCode extension and have noticed that the Flex Spi Clk is not running at our desired 100MHz speed.
We are using XIP from flash and have configured the "flexspi_nor_config_t" with a "serialClkFreq" of "kFlexSpiSerialClk_100MHz". 
However, when we readout the clock in our main function we get a value of 37.4 MHz.

I also checked the following, CLK_SEL register of 
CCM_CSCMR1 which indicates PLL3 PFD0 (running at 262MHz since the divider is 33 when reading out 0x400D_80F0).

Finally, I also checked FLEXSPI_PODF which showed 7 which results in our 37.4MHz signal. 

I also checked that this struct "flexspi_nor_config_t" is located at "boot_hdr.conf" in the map file and this also seems correct.

My question is how is the CCM configured during boot from the ROM memory? What is going wrong here and how can I further troubleshoot this issue?

Please let me know if you require any additional information.

Kind regards,

Maxim

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Maximvda
Contributor III

The issue is caused by the debugging processing when using the VS Code extension. An additional reset is required for the Clocks to be configured correctly. 
This behaviour can be obtained by setting an addition parameter in the mcuxpresso-tools.json file : "resetAfterLoad": true

@kerryzhou Thanks for your time. This is the solution for our problem

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Maximvda
Contributor III

The issue is caused by the debugging processing when using the VS Code extension. An additional reset is required for the Clocks to be configured correctly. 
This behaviour can be obtained by setting an addition parameter in the mcuxpresso-tools.json file : "resetAfterLoad": true

@kerryzhou Thanks for your time. This is the solution for our problem

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EdwinHz
NXP TechSupport
NXP TechSupport

Hi @Maximvda,

Could you please let us know the specific i.MX RT part number you are using?

Thanks

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Maximvda
Contributor III

Hi @EdwinHz 

we are using the IMXRT1061CVJ5B

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @Maximvda ,

  Do you try the SDK demo code, then modify the FCB to the 100Mhz on your side, just like this:

kerryzhou_0-1704363124474.png

 

Whether it works Ok or not, this method works on my side.

If you still have issues about it, you can tell us your used RT1060 board and the SDK version, and the detail code modification on your side.

Best Regards,

kerry

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Maximvda
Contributor III

Hi Kerryzhou,

No, we are running our own application on a custom board. The SDK version we are using is the following:

- name: mcux-sdk
revision: MCUX_2.14.0
path: mcuxsdk/core
- name: FreeRTOS-Kernel
revision: MCUX_2.14.0
path: mcuxsdk/rtos/freertos/freertos-kernel
- name: CMSIS_5
path: mcuxsdk/core/CMSIS
revision: MCUX_2.13.0



The setup of our application is very similar to the setup of example projects which use the MCUExpresso VSCode extension 
https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools...

We then move the file "evkbmimxrt1060_flexspi_nor_config" outside of the sdk as we needed to modify it and linked this new file in our CMakeLists as shown in the screenshot below.

Maximvda_0-1704370770138.png

Please let me know if I should try it with a specific example project (preferably one from VSCode extension).

I performed some additional tests with the following results:

serialClkFreq = kFlexSpiSerialClk_80MHz -> Results in Clk speed of 43 MHz
serialClkFreq = kFlexSpiSerialClk_100MHz -> Results in Clk speed of 37 MHz
serialClkFreq = kFlexSpiSerialClk_120MHz -> Results in Clk speed of 65 MHz
serialClkFreq = kFlexSpiSerialClk_133MHz -> Results in Clk speed of 52 MHz
serialClkFreq = kFlexSpiSerialClk_166MHz -> Results in Clk speed of 65 MHz

For each of these cases CLK_SEL register of CCM_CSCMR1 which indicates PLL3 PFD0 (running at 262MHz since the divider is 33 when reading out 0x400D_80F0). So the ROM bootloader is only changing the divider FLEXSPI_PODF

 

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @Maximvda ,

  Thanks for your updated information.

   Seems related to the code configuration.

  Which demo you are testing now in the SDK, please let me know.

As I want to check, except the FCB to define the flexSPI clock, whether your app code clock side reconfigure the flexspi clock again.

Best Regards,

kerry

    

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Maximvda
Contributor III

Hi @kerryzhou ,

I've been doing some more testing and I have tried the LPUART_EDMA_RB_TRANSFER example using the MCUXpresso IDE. With this example I do indeed get the correct frequency. For 100 MHz I see that the PLL3_PFD0 divider is (12*18) so 720 MHz and then FLEXSPI_PODF (7) -> 102 MHz.
For a setting of 80 MHz I see the PLL3_PFD0 divider is (18*18) so 480 MHz and then FLEXSPI_PODF (6) -> 80 MHz.

I also compared the memory region 0x60000000, 1000 using that example and our own code and for both I get exactly the same memory. To my understanding this is the place where the ROM loads it's config from.

Then I also checked on program entry the addresses: 0x400FC01C and 0x400D80F0 to check the  PLL3_PFD0 and FLEXSPI_PODF divider. This resulted in the values 1729298433 and 253371169 which translates to a PLL3_PFD0 divider (33*18) and FLEXSPI_PODF (7) giving the 37 MHz frequency.
So this would mean the dividers are not changed by our code but even before our code is started.

Any idea's on how to proceed are welcome.

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @Maximvda ,

  So, you mean, the SDK MCUXPresso IDE project, that works OK.

  But, the SDK VSCODE project can't work correct, right?

  Check this code, do you enable it in your VScode or not?

MCUXpresso project didn't enable it:

kerryzhou_0-1704701968139.png

Best Regards,

kerry

 

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Maximvda
Contributor III

Hi @kerryzhou 

Correct, I tried with the SDK MCUXPresso IDE project, that works OK.
I then tried the same example using the MCUXpresso extension for VSCod, selected the build variant "flexspi_nor_debug" and that fails, giving me wrong clock configurations.

I also checked the code you mention and that code is disabled. The Define XIP_EXTERNAL_FLASH is defined and == 1.

Best regards,

Maxim

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @Maximvda ,

  So, your test result:

serialClkFreq = kFlexSpiSerialClk_80MHz -> Results in Clk speed of 43 MHz

serialClkFreq = kFlexSpiSerialClk_100MHz -> Results in Clk speed of 37 MHz
serialClkFreq = kFlexSpiSerialClk_120MHz -> Results in Clk speed of 65 MHz
serialClkFreq = kFlexSpiSerialClk_133MHz -> Results in Clk speed of 52 MHz
serialClkFreq = kFlexSpiSerialClk_166MHz -> Results in Clk speed of 65 MHz
Just change the FCB area, I mean this area:
kerryzhou_0-1704794461019.png

 

Right?

Even the simple demo: hello_world also reproduce the issues?

Please help to confirm it, then I will test it on my MIMXRT1060-EVK board.

Best Regards,

Kerry

 
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Maximvda
Contributor III

Hi @kerryzhou,

We have just tested the hello_world example with our https://www.nxp.com/part/MIMXRT1060-EVKB#/ 

We also changed the FCB area and got exactly the same results, so you should be able to reproduce it if you are using MCUXPRESSO-VSC . 

Kind regards,

Maxim