FLEXSPI prefetch alignment

[stefanct]

I am working on evaluating/implementing different options to attach
external hardware to the RT1020 for our future product. Currently I try
to find out how much performance loss is incurred when using a PSRAM for
parts of the program's data instead of the internal SRAM/DTC when the
PSRAM is attached via (quad) SPI. I have the basic communication
working, have set up my own LUT according to the datasheet and the
correct AHB indices etc. I can read and write from the PSRAM via
direct/AHB memory accesses.

However, one major obstacle in actually using it came up during
testing. My current understanding is that the PSRAM wraps around if a
transfer crosses a 1024 bytes page boundary. This is an issue if
prefetching is enabled because this causes reads that cross these
boundaries if the start address of the read is within the last N-1
bytes for prefetching blocks of size N. In that case the read partially
returns wrong data towards the end of the read (i.e., the data located
at the beginning of the page where the read started instead of the
following page). I can send you pictures of the signal trace or other
additional information if anything is unclear.

Since I cannot limit the start addresses of the reads, FLEXSPI has to
deal with this to allow for enabling prefetching. I have tried
understanding as much of the FLEXSPI configuration as possible by
cross-referencing TRMs from multiple members of the RT family, the ANs

I am working on evaluating/implementing different options to attach
external hardware to the RT1020 for our future product. Currently I try
to find out how much performance loss is incurred when using a PSRAM for
parts of the program's data instead of the internal SRAM/DTC when the
PSRAM is attached via (quad) SPI. I have the basic communication
working, have set up my own LUT according to the datasheet and the
correct AHB indices etc. I can read and write from the PSRAM via
direct/AHB memory accesses.

However, one major obstacle in actually using it came up during
testing. My current understanding is that the PSRAM wraps around if a
transfer crosses a 1024 bytes page boundary. This is an issue if
prefetching is enabled because this causes reads that cross these
boundaries if the start address of the read is within the last N-1
bytes for prefetching blocks of size N. In that case the read partially
returns wrong data towards the end of the read (i.e., the data located
at the beginning of the page where the read started instead of the
following page). I can send you pictures of the signal trace or other
additional information if anything is unclear.

Since I cannot limit the start addresses of the reads, FLEXSPI has to
deal with this to allow for enabling prefetching. I have tried
understanding as much of the FLEXSPI configuration as possible by
cross-referencing TRMs from multiple members of the RT family, the ANs
on related topics such as 12239, 12437, 13028 and also the insightful
blog posts by @jay_heng (e.g.,
https://www.cnblogs.com/henjay724/p/14742519.html) but to no avail. The
only thing that came up during my research is the ALIGNMENT field of
AHBCR described in RT1020 RM that looks like it might be intended to
solve this problem. Unfortunately, I could not find any more
information than the one sentence in the register description and some
preliminary testing of setting the respective bits didn't show any
effect.

I am looking for any additional information or insights on how to confine the
AHB-incurred reads to the PSRAM's page boundaries? Thanks!

[HangZhang]

Hi @stefanct 

Thanks for your interest in NXP MIMXRT series.

Please configure the cross page configuration of PSRAM. The cross page configuration of PSRAM is for the PSRAM side, not for the FLEXSPI controller. You can configure cross page configuration according to the PSRAM manual.

Best regards,

Hang

[stefanct]

Hi @HangZhang,
I'd love to do that but the only configuration in the PSRAM in this regard is a switch between 32 and 1024 byte wrapping. Unfortunately, the smaller PSRAMs do not support the linear burst mode that HYPERRAM devices support. Basically they only support the wrapped burst mode and that's my problem.

The PSRAM we are using is an IS66WVS4M8BLL-104NLI:
https://www.issi.com/WW/pdf/66-67WVS4M8ALL-BLL.pdf
The QSPI PSRAM that NXP explicitly mentions as supported in AN13028 behaves the same, i.e., either 32 or 1024 wrapped burst.

[HangZhang]

Hi, @stefanct 

As your mentioned, in AN13028, One PSRAM device used is APS6404L-3SQR. And according to APS6404L-3SQR user guide page 23.

Note 1: Only Linear Burst allows page boundary crossing. Frequency limits are therefore
133MHz (PKG VDD= 3.0V+-10%), 109MHz(PKG VDD= 3.3V+-10%) max for Wrap 32 Bytes, and
84MHz for Linear Burst commands cross page boundary.

So please double check if the PSRAM you used for testing supports page boundary crossing.

Best regards,
Hang

[stefanct]

My bad. I didn't check what the last character of the apmemory part numbers mean and looked at the APS6404L-3SQN where the last character is only specified as "special feature". In the APS6404L-3SQR datasheet it is specified as RBX (row boundary crossing).

In any case, the PSRAM I am currently testing does not have that feature and my original question still remains: Is there a way to limit AHB burst accesses to not cross arbitrary/1k address boundaries on the MCU side?

[HangZhang · Accepted solution]

Hi @stefanct 

Sorry, there is not a way to limit AHB burst accesses to not cross arbitrary/1k address boundaries on the MCU side.

Best regards,
Hang