Adding SDRAM drivers and Powermode switch to a team project.

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Adding SDRAM drivers and Powermode switch to a team project.

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VolcanicCheese
Contributor III

I was testing things using example projects. I was wondering why there is an error when I implement the sdram and powermode switch projects together. The file below is the project that is broken. Is this problem occurring because we cannot access the sdram when we try to change the frequency of the sdram? We are using the rt1020 dev board. Thank you so much!

Details of the project:

idle_task.c switches the powermode. imag_task.c switches the sdram. The init of all the drivers is in peripheral.c. The sdram code and powermode switch code comes from the example sdk project given in the NXP IDE. The code for the sdram and powermode are in the driver folder. We wrote our custom sdram access code and it is tested correctly. it works fine without the powermode code.

This is the link to my team's project: https://github.com/AA-CubeSat-Team/soci_cdh_rtos/tree/dev/cdh_prototype

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @VolcanicCheese 

   When you change the power mode to the low power mode, and you also need to use the SDRAM, you need to make sure the SEMC related clock can also be used or have a limit at first.

  BTW, please refer to this application note:

How to use i.MX RT Low Power Feature (nxp.com)

Usually under any RUN mode, if the SPI Flash or SDRAM are used to store code or data, changing the root
clock’s frequency is not recommended. It is dangerous to R/W SPI Flash or SDRAM while changing their clock
source and frequency. If these operations have to do, the code should be run in On-Chip RAM.

 

If the code run in SDRAM and user wants to enter Suspend mode. SDRAM needs to wait a STOP signal to enter
self-refresh mode. Here if a STOP request is sent to SDRAM and polling for the acknowledge bit to be asserted,
the bit asserted might never get . Because the code is running on SDRAM and the transaction on SDRAM can’t
STOP. In this case, the code or data should be run in SPI Flash or On-chip RAM.

More details, please check that AN.

 

Wish it helps you!

Best Regards,

Kerry

 

 

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858 次查看
kerryzhou
NXP TechSupport
NXP TechSupport

Hi @VolcanicCheese 

   When you change the power mode to the low power mode, and you also need to use the SDRAM, you need to make sure the SEMC related clock can also be used or have a limit at first.

  BTW, please refer to this application note:

How to use i.MX RT Low Power Feature (nxp.com)

Usually under any RUN mode, if the SPI Flash or SDRAM are used to store code or data, changing the root
clock’s frequency is not recommended. It is dangerous to R/W SPI Flash or SDRAM while changing their clock
source and frequency. If these operations have to do, the code should be run in On-Chip RAM.

 

If the code run in SDRAM and user wants to enter Suspend mode. SDRAM needs to wait a STOP signal to enter
self-refresh mode. Here if a STOP request is sent to SDRAM and polling for the acknowledge bit to be asserted,
the bit asserted might never get . Because the code is running on SDRAM and the transaction on SDRAM can’t
STOP. In this case, the code or data should be run in SPI Flash or On-chip RAM.

More details, please check that AN.

 

Wish it helps you!

Best Regards,

Kerry