I am building an SD driver.
It is working, but I have not found a clear description of the access order of the CCM_CSCDR1 register.
If anyone knows, I would appreciate a comment.
I am accessing them in the following order
1: Write CG0, CG1, CG2, of CCM_CCGR6
2: Write MOD_EN_USDHC in CCM_CMEOR
3: Write USDHC1_CLK_SEL in CCM_CSCMR1
4: Write USDHC1_PODF in CCM_CSCDR1
However, CCM_CSCMR1 and CCM_CSCDR1 have the following description.
Any change on the above multiplexer will have to be done while the module that its clock is affected is not functional and the clock is gated. If the change will be done during operation of the module, then it is not guaranteed that the modules operation will not be harmed.
Any change on the above dividers will have to be done while the module that its clock is affected is not functional and the affected clock is gated. If the change will be done during operation of the module, then it is not guaranteed that the modules operation will not be harmed.
I think 1 and 2 need to be done after 3 and 4, but what is the correct order?
