Hello,
I want to use BBNSM(Battery-Backed Non-Secure Module) RTC from U-Boot on i.MX 8ULP.
The smart way would be to use RPMsg, but it's not implemented in U-Boot.
However, I can't access the BBNSM register from the Arm Cortex A35. Is there an exclusive lock with the Arm Cortex-M33? Since the power_mode_switch is working on the M33, the BBNSM RTC is used.
BBNSM is mapped to PBRIDGE0(Peripheral Bridge 0) on A35. I tried to see if I could use BBNSM with the A35.
I tried to read BBNSM_RTC_LS(BBNSM Real-Time Counter LS Register) but couldn't.
<pre>
=> md.l 0x28038040 1
"Synchronous Abort" handler, esr 0x96000210
elr: 000000008029b2a4 lr : 000000008029b1f4 (reloc)
elr: 00000000a5eef2a4 lr : 00000000a5eef1f4
x0 : 0000000000000009 x1 : 00000000fffffffe
x2 : 00000000a4e49458 x3 : 0000000000000020
x4 : 00000000ffffffff x5 : 00000000a4e491e8
x6 : 0000000000000030 x7 : 00000000a4e493a0
x8 : 0000000000000010 x9 : 0000000090a65063
x10: 00000000ffffffd8 x11: 0000000000000010
x12: 0000000000000006 x13: 000000000001869f
x14: 00000000a4e497c0 x15: 0000000000000021
x16: 00000000a5e6eb0c x17: 0000000000000000
x18: 00000000a4e51d40 x19: 0000000000000004
x20: 0000000000000004 x21: 0000000000000001
x22: 0000000028038040 x23: 00000000a4e49459
x24: 0000000000000000 x25: 00000000a4e49408
x26: 00000000a5f0ec2b x27: 0000000000000008
x28: 0000000000000004 x29: 00000000a4e493a0
Code: 2a0403f3 17ffffcb 7100129f 54000181 (b94002c3)
Resetting CPU ...
resetting ...
</pre>
PCC_BBNSM(PCC BBNSM Register) is 0xC0000000(PR=1, CGC=1), so it's
ready to use.
<pre>
=> md.l 0x280300e0 1 280300e0: c0000000 ....
</pre>
I've also tried using a Linux kernel, but I'm unable to access it
either. The driver used was rtc-nxp-bbnsm.c below.
https://lore.kernel.org/linux-arm-kernel/20230215024117.3357341-1-ping.bai@nxp.com/T/
Thanks,
mizo
