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u-boot 2015.04 lvds 24 bit color issue

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u-boot 2015.04 lvds 24 bit color issue

‎04-18-2023 03:29 AM
787 Views
tgl
Contributor III

I'm porting an u-boot 2015.04 on an imx6 board, I can't use a newer one because it has a raw nand, and it seems to be the only one compatible with 4.1.15 kernel. All is working expect for the LVDS display, which seems to be displaying the wrong colors, after booting Linux the display is working fine, only difference is that in the kernel it's 32bpp, but I have used fbset to change it to 24 also in the kernel and to 16 and its working fine. 

I've tried to debug the issue by changing various settings in the setup_display function, I've also debugged the framebuffer, switching the inputs and the outputs from 16bit input to 24bit input to 32bit, but I get the same result. In the memory for example at 24bit, the colors are correct (byte 1, byte 2, byte 3), I've also checked the IPU mapping, modified it, added 32bit mapping but nothing seems to fix the issue. I've checked the iomux, the LVDS pins are the same, there is no flickering so I think the timings are correct, they are the same as on Linux.

The only thing I could think is that the channel is 18bit and not 24, and this is why some colors do not display ok, in general the BLUE is ok, but ORANGE for example becomes RED, in any case I've attached some pictures so you can see the difference between u-boot and kernel, I've made sure channel is set to 24bit though, double checked and also tampered with mxc_ccm->cs2cdr making sure JEIDA, 24bit is selected, tried also 18bit, same thing, but colors are worse. 

Here is the setup display function:

 

static void setup_display(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
int reg;

setup_iomux_display_backlight(); /* Disable to avoid backlight flash on start */
enable_ipu_clock();
imx_setup_hdmi();

/* Turn on IPU LDB DI0 clocks */
setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);

/* Switch LDB DI0 to PLL5 (Video PLL) */
clrsetbits_le32(&mxc_ccm->cs2cdr,
MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
(3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));

/* LDB clock div by 3.5 */
clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);

/* DI0 clock derived from ldb_di0_clk */
clrsetbits_le32(&mxc_ccm->chsccdr,
MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
(CHSCCDR_CLK_SEL_LDB_DI0 <<
MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
);

/* Enable both LVDS channels, both connected to DI0. */
writel(IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA |
IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA |
IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 |
IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
&iomux->gpr[2]);

clrsetbits_le32(&iomux->gpr[3],
IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
IOMUXC_GPR3_LVDS1_MUX_CTL_MASK,
(IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
(IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
);
 
the display_info_t:
 
#define MHZ2PS(f) (1000000/(f))
 
struct display_info_t const displays[] = {{
.bus = -1,
.addr = 0,
.pixfmt = IPU_PIX_FMT_RGB24,
.detect = NULL,
.enable = NULL,
.mode = {
.name = "LDB-WVGA",
.refresh = 59,
.xres = 800,
.yres = 480,
.pixclock = MHZ2PS(28.160),
.left_margin = 85,
.right_margin = 20,
.upper_margin = 32,
.lower_margin = 8,
.hsync_len = 2,
.vsync_len = 2,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
} }};

 

Linux fbset output:

mode "800x480-59"
# 28.160 MHz, H: 31.048 kHz, V: 59.478 Hz
geometry 800 480 800 480 32
timings 35511 85 20 32 8 2 2
accel false
rgba 8/16,8/8,8/0,8/24
endmode

Linux dts entry:

lvds-channel@0 {
fsl,data-mapping = "jeida";
fsl,data-width = <24>;
crtc = "ipu1-di0";
primary;
status = "okay";

display-timings {
native-mode = <&timing0>;
timing0: mitsubishi {
clock-frequency = <28160000>;
hactive = <800>;
vactive = <480>;
hback-porch = <85>;
hfront-porch = <20>;
vback-porch = <32>;
vfront-porch = <8>;
hsync-len = <2>;
vsync-len = <2>;
linux,phandle = <&timing0>;
};
};
};

 

u-boot output:

U-Boot 2015.04 (Apr 17 2023 - 16:17:13)

CPU: Freescale i.MX6Q rev1.5 at 792 MHz
CPU: Temperature 28 C
Reset cause: WDOG
Board: MX6QP-CES-Coreboard revA
I2C: ready
DRAM: 2 GiB
mxc_ccm->CCGR3 = 0x020C4074 0x3FF03003
mxc_ccm->CCGR3: 00110000 00001111
mxc_ccm->CCGR3: 00110000 00000011
mxc_ccm->cs2cdr = 0x020C402C 0x007236C1
mxc_ccm->chsccdr = 0x020C4034 0x0002A153
iomux->gpr[2] = 0x020E0008 0x000003F5
iomux->gpr[3] = 0x020E000C 0x01E00000
iomux->gpr[4] = 0x020E0010 0xF00000CF
NAND: 1024 MiB
Using default environment

Display: LDB-WVGA (800x480)
ipu_clk = 264000000
ldb_clk[0] = 65000000
ldb_clk[1] = 65000000
read BS_CLKGEN0 div:0, final_rate:4224000000, prate:264000000
read BS_CLKGEN0 div:0, final_rate:4224000000, prate:264000000
ipu_dc_map_config -> map = 0 byte_num = 0 offset = 7 mask = ff
ipu_dc_map_config -> map = 0 byte_num = 1 offset = 15 mask = ff
ipu_dc_map_config -> map = 0 byte_num = 2 offset = 23 mask = ff
ipu_dc_map_config -> map = 1 byte_num = 0 offset = 5 mask = fc
ipu_dc_map_config -> map = 1 byte_num = 1 offset = 11 mask = fc
ipu_dc_map_config -> map = 1 byte_num = 2 offset = 17 mask = fc
ipu_dc_map_config -> map = 2 byte_num = 0 offset = 15 mask = ff
ipu_dc_map_config -> map = 2 byte_num = 1 offset = 23 mask = ff
ipu_dc_map_config -> map = 2 byte_num = 2 offset = 7 mask = ff
ipu_dc_map_config -> map = 3 byte_num = 0 offset = 4 mask = f8
ipu_dc_map_config -> map = 3 byte_num = 1 offset = 10 mask = fc
ipu_dc_map_config -> map = 3 byte_num = 2 offset = 15 mask = f8
ipu_dc_map_config -> map = 4 byte_num = 0 offset = 5 mask = fc
ipu_dc_map_config -> map = 4 byte_num = 1 offset = 13 mask = fc
ipu_dc_map_config -> map = 4 byte_num = 2 offset = 21 mask = fc
IPU DMFC NORMAL mode: 1(0~1), 5B(4,5), 5F(6,7)
mxcfb_init_fbinfo: 4 640 112 524
Framebuffer structures at: fbi=0x8ef9a7a8 mxcfbi=0x8ef9a9b8
allocated fb @ paddr=0x8EF9CD60, size=2304000.
Channel already disabled 9
Channel already uninitialized 9
setup_disp_channel1 called
bpp_to_pixfmt: 24
mxc_ipuv3_fb: bpp_to_pixfmt -> IPU_PIX_FMT_BGR24
init channel = 9
format_to_colorspace -> returning RGB
format_to_colorspace -> returning RGB


COLOR SPACE SETUP 2 2

IN PIXEL FORMAT IS OK
OUT PIXEL FORMAT IS OK
pixclock = 28160000 Hz
IT IS IPU_PIX_FMT_RGB24!!!
panel size = 800 x 480
pixel clk = 28160000Hz
h_total = 907 800+2+85+20
v_total = 522 480+2+32+8
read BS_CLKGEN0 div:0, final_rate:1040000000, prate:65000000
ipu_pixfmt_to_map - we set it to IPU_PIX_FMT_RGB24
Signal NOT interlaced
setup_disp_channel2: 95ffcff 800 480 2400 8ef9cd60 8f0b6160
bpp_to_pixfmt: 24
mxc_ipuv3_fb: bpp_to_pixfmt -> IPU_PIX_FMT_BGR24
We set the bits/pixel 1, pix format 7, burst size 19
We setup the offsets: red_width = 7 red_offset = 16
We setup the offsets: green_width = 7 green_offset = 8
We setup the offsets: blue_width = 7 blue_offset = 0
Do we have uv_stride: 0
u_offset = 0 v_offset = 0
initializing idma ch 23 @ 027005c0
ch 23 word 0 - 00000000 00000000 00000000 E0000800 00077C63
ch 23 word 1 - 91E16C2C 023BE735 20E4C000 FFF257C0 000C0110
PFS 0x7, BPP 0x1, NPB 0x13
FW 799, FH 479, Stride 2399
Width0 7+1, Width1 7+1, Width2 7+1, Width3 7+1, Offset0 16, Offset1 8, Offset2 0, Offset3 24
IPU_CONF = 0x00000660
IDMAC_CONF = 0x0000002F
IDMAC_CHA_EN1 = 0x00800000
IDMAC_CHA_EN2 = 0x00000000
IDMAC_CHA_PRI1 = 0x18800003
IDMAC_CHA_PRI2 = 0x00000000
IPU_CHA_DB_MODE_SEL0 = 0x00800000
IPU_CHA_DB_MODE_SEL1 = 0x00000000
DMFC_WR_CHAN = 0x00000090
DMFC_WR_CHAN_DEF = 0x202020F6
DMFC_DP_CHAN = 0x00009694
DMFC_DP_CHAN_DEF = 0x2020F6F6
DMFC_IC_CTRL = 0x00000002
IPU_FS_PROC_FLOW1 = 0x00000000
IPU_FS_PROC_FLOW2 = 0x00000000
IPU_FS_PROC_FLOW3 = 0x00000000
IPU_FS_DISP_FLOW1 = 0x00000000
Framebuffer at 0x8ef9cd60
We are in 8 VIDEO_DATA_FORMAT = 4
We write GDF_24BIT_888RGB to framebuffer

 

kernel output:

[ 0.203042] imx-ipuv3 2400000.ipu: <ipu_probe>
[ 0.203078] imx-ipuv3 2400000.ipu: revision is IPUv3H
[ 0.203288] imx-ipuv3 2400000.ipu: IPU CM Regs = f005e000
[ 0.203302] imx-ipuv3 2400000.ipu: IPU IC Regs = f0066000
[ 0.203315] imx-ipuv3 2400000.ipu: IPU IDMAC Regs = f006e000
[ 0.203327] imx-ipuv3 2400000.ipu: IPU DP Regs = f0076000
[ 0.203339] imx-ipuv3 2400000.ipu: IPU DC Regs = f007e000
[ 0.203349] imx-ipuv3 2400000.ipu: IPU DMFC Regs = f0086000
[ 0.203360] imx-ipuv3 2400000.ipu: IPU DI0 Regs = f008c000
[ 0.203372] imx-ipuv3 2400000.ipu: IPU DI1 Regs = f008e000
[ 0.203383] imx-ipuv3 2400000.ipu: IPU SMFC Regs = f0096000
[ 0.203394] imx-ipuv3 2400000.ipu: IPU CSI0 Regs = f009e000
[ 0.203404] imx-ipuv3 2400000.ipu: IPU CSI1 Regs = f00a6000
[ 0.203417] imx-ipuv3 2400000.ipu: IPU CPMem = f0100000
[ 0.203427] imx-ipuv3 2400000.ipu: IPU TPMem = f0140000
[ 0.203439] imx-ipuv3 2400000.ipu: IPU DC Template Mem = f0180000
[ 0.203450] imx-ipuv3 2400000.ipu: IPU VDI Regs = f00a8000
[ 0.219656] imx-ipuv3 2400000.ipu: IPU DMFC NORMAL mode: 1(0~1), 5B(4,5), 5F(6,7)
[ 0.219674] imx-ipuv3 2400000.ipu: ipu_clk = 264000000
[ 0.220664] ipu_task_thread: sched_setaffinity cpu:0.
[ 0.220751] ipu_task_thread: sched_setaffinity cpu:0.
[ 0.220813] imx-ipuv3 2800000.ipu: <ipu_probe>
[ 0.220846] imx-ipuv3 2800000.ipu: revision is IPUv3H
[ 0.221069] imx-ipuv3 2800000.ipu: IPU CM Regs = f00aa000
[ 0.221085] imx-ipuv3 2800000.ipu: IPU IC Regs = f00ac000
[ 0.221098] imx-ipuv3 2800000.ipu: IPU IDMAC Regs = f00ae000
[ 0.221110] imx-ipuv3 2800000.ipu: IPU DP Regs = f00b0000
[ 0.221120] imx-ipuv3 2800000.ipu: IPU DC Regs = f00b2000
[ 0.221131] imx-ipuv3 2800000.ipu: IPU DMFC Regs = f00b4000
[ 0.221141] imx-ipuv3 2800000.ipu: IPU DI0 Regs = f00b6000
[ 0.221152] imx-ipuv3 2800000.ipu: IPU DI1 Regs = f00b8000
[ 0.221162] imx-ipuv3 2800000.ipu: IPU SMFC Regs = f00ba000
[ 0.221173] imx-ipuv3 2800000.ipu: IPU CSI0 Regs = f00bc000
[ 0.221183] imx-ipuv3 2800000.ipu: IPU CSI1 Regs = f00be000
[ 0.221193] imx-ipuv3 2800000.ipu: IPU CPMem = f01c0000
[ 0.221203] imx-ipuv3 2800000.ipu: IPU TPMem = f0160000
[ 0.221213] imx-ipuv3 2800000.ipu: IPU DC Template Mem = f0200000
[ 0.221223] imx-ipuv3 2800000.ipu: IPU VDI Regs = f00fc000
[ 0.239649] imx-ipuv3 2800000.ipu: IPU DMFC NORMAL mode: 1(0~1), 5B(4,5), 5F(6,7)
[ 0.239667] imx-ipuv3 2800000.ipu: ipu_clk = 264000000
[ 0.240229] ipu_task_thread: sched_setaffinity cpu:0.
[ 0.240324] ipu_task_thread: sched_setaffinity cpu:0.
[ 0.291598] imx-ipuv3 2400000.ipu: Channel already disabled 9
[ 0.291608] imx-ipuv3 2400000.ipu: Channel already uninitialized 9
[ 0.301239] imx-ipuv3 2400000.ipu: init channel = 9
[ 0.301253] imx-ipuv3 2400000.ipu: ipu busfreq high requst.
[ 0.301283] imx-ipuv3 2400000.ipu: IPU_CONF = 0x00000000
[ 0.301290] imx-ipuv3 2400000.ipu: IDMAC_CONF = 0x0000002F
[ 0.301298] imx-ipuv3 2400000.ipu: IDMAC_CHA_EN1 = 0x00000000
[ 0.301306] imx-ipuv3 2400000.ipu: IDMAC_CHA_EN2 = 0x00000000
[ 0.301313] imx-ipuv3 2400000.ipu: IDMAC_CHA_PRI1 = 0x18800003
[ 0.301321] imx-ipuv3 2400000.ipu: IDMAC_CHA_PRI2 = 0x00000000
[ 0.301327] imx-ipuv3 2400000.ipu: IDMAC_BAND_EN1 = 0x00000000
[ 0.301334] imx-ipuv3 2400000.ipu: IDMAC_BAND_EN2 = 0x00000000
[ 0.301341] imx-ipuv3 2400000.ipu: IPU_CHA_DB_MODE_SEL0 = 0x00000000
[ 0.301349] imx-ipuv3 2400000.ipu: IPU_CHA_DB_MODE_SEL1 = 0x00000000
[ 0.301356] imx-ipuv3 2400000.ipu: IPU_CHA_TRB_MODE_SEL0 = 0x00000000
[ 0.301363] imx-ipuv3 2400000.ipu: IPU_CHA_TRB_MODE_SEL1 = 0x00000000
[ 0.301371] imx-ipuv3 2400000.ipu: DMFC_WR_CHAN = 0x00000090
[ 0.301378] imx-ipuv3 2400000.ipu: DMFC_WR_CHAN_DEF = 0x202020F6
[ 0.301386] imx-ipuv3 2400000.ipu: DMFC_DP_CHAN = 0x00009694
[ 0.301393] imx-ipuv3 2400000.ipu: DMFC_DP_CHAN_DEF = 0x2020F6F6
[ 0.301399] imx-ipuv3 2400000.ipu: DMFC_IC_CTRL = 0x00000002
[ 0.301407] imx-ipuv3 2400000.ipu: IPU_FS_PROC_FLOW1 = 0x00000000
[ 0.301413] imx-ipuv3 2400000.ipu: IPU_FS_PROC_FLOW2 = 0x00000000
[ 0.301419] imx-ipuv3 2400000.ipu: IPU_FS_PROC_FLOW3 = 0x00000000
[ 0.301425] imx-ipuv3 2400000.ipu: IPU_FS_DISP_FLOW1 = 0x00000000
[ 0.301431] imx-ipuv3 2400000.ipu: IPU_VDIC_VDI_FSIZE = 0x00000000
[ 0.301437] imx-ipuv3 2400000.ipu: IPU_VDIC_VDI_C = 0x00000000
[ 0.301443] imx-ipuv3 2400000.ipu: IPU_IC_CONF = 0x00000000
[ 0.301453] imx-ipuv3 2400000.ipu: panel size = 800 x 480
[ 0.301460] imx-ipuv3 2400000.ipu: pixel clk = 28160000
[ 0.301535] imx-ipuv3 2400000.ipu: use special clk parent
[ 0.301557] imx-ipuv3 2400000.ipu: round pixel clk:28159999
[ 0.313238] imx-ipuv3 2400000.ipu: div:1
[ 0.313287] imx-ipuv3 2400000.ipu: initializing idma ch 23 @ f01005c0
[ 0.313300] imx-ipuv3 2400000.ipu: initializing idma ch 23 @ f0101140 sub cpmem
[ 0.313323] imx-ipuv3 2400000.ipu: ch 23 word 0 - 00000000 00000000 00000000 E0000000 00077C63
[ 0.313334] imx-ipuv3 2400000.ipu: ch 23 word 1 - 0D0C0000 01A18000 00E3C000 FFF31FC0 00006208
[ 0.313340] imx-ipuv3 2400000.ipu: PFS 0x7,
[ 0.313346] imx-ipuv3 2400000.ipu: BPP 0x0,
[ 0.313353] imx-ipuv3 2400000.ipu: NPB 0xf
[ 0.313359] imx-ipuv3 2400000.ipu: FW 799,
[ 0.313365] imx-ipuv3 2400000.ipu: FH 479,
[ 0.313371] imx-ipuv3 2400000.ipu: EBA0 0x68600000
[ 0.313378] imx-ipuv3 2400000.ipu: EBA1 0x68600000
[ 0.313384] imx-ipuv3 2400000.ipu: Stride 3199
[ 0.313390] imx-ipuv3 2400000.ipu: scan_order 0
[ 0.313396] imx-ipuv3 2400000.ipu: uv_stride 8712
[ 0.313403] imx-ipuv3 2400000.ipu: u_offset 0x0
[ 0.313409] imx-ipuv3 2400000.ipu: v_offset 0x0
[ 0.313415] imx-ipuv3 2400000.ipu: Width0 7+1,
[ 0.313422] imx-ipuv3 2400000.ipu: Width1 7+1,
[ 0.313428] imx-ipuv3 2400000.ipu: Width2 7+1,
[ 0.313434] imx-ipuv3 2400000.ipu: Width3 7+1,
[ 0.313440] imx-ipuv3 2400000.ipu: Offset0 8,
[ 0.313445] imx-ipuv3 2400000.ipu: Offset1 16,
[ 0.313451] imx-ipuv3 2400000.ipu: Offset2 24,
[ 0.313457] imx-ipuv3 2400000.ipu: Offset3 0
[ 0.347381] imx-ipuv3 2400000.ipu: DC stop timeout - 3 * 10ms
[ 0.347426] imx-ipuv3 2400000.ipu: ipu busfreq high release.
[ 0.347500] imx-ipuv3 2400000.ipu: init channel = 9
[ 0.347510] imx-ipuv3 2400000.ipu: ipu busfreq high requst.
[ 0.347534] imx-ipuv3 2400000.ipu: IPU_CONF = 0x00000000
[ 0.347541] imx-ipuv3 2400000.ipu: IDMAC_CONF = 0x0000002F
[ 0.347548] imx-ipuv3 2400000.ipu: IDMAC_CHA_EN1 = 0x00000000
[ 0.347554] imx-ipuv3 2400000.ipu: IDMAC_CHA_EN2 = 0x00000000
[ 0.347562] imx-ipuv3 2400000.ipu: IDMAC_CHA_PRI1 = 0x18800003
[ 0.347568] imx-ipuv3 2400000.ipu: IDMAC_CHA_PRI2 = 0x00000000
[ 0.347574] imx-ipuv3 2400000.ipu: IDMAC_BAND_EN1 = 0x00000000
[ 0.347580] imx-ipuv3 2400000.ipu: IDMAC_BAND_EN2 = 0x00000000
[ 0.347586] imx-ipuv3 2400000.ipu: IPU_CHA_DB_MODE_SEL0 = 0x00000000
[ 0.347592] imx-ipuv3 2400000.ipu: IPU_CHA_DB_MODE_SEL1 = 0x00000000
[ 0.347598] imx-ipuv3 2400000.ipu: IPU_CHA_TRB_MODE_SEL0 = 0x00000000
[ 0.347605] imx-ipuv3 2400000.ipu: IPU_CHA_TRB_MODE_SEL1 = 0x00000000
[ 0.347611] imx-ipuv3 2400000.ipu: DMFC_WR_CHAN = 0x00000090
[ 0.347617] imx-ipuv3 2400000.ipu: DMFC_WR_CHAN_DEF = 0x202020F6
[ 0.347625] imx-ipuv3 2400000.ipu: DMFC_DP_CHAN = 0x000096D4
[ 0.347632] imx-ipuv3 2400000.ipu: DMFC_DP_CHAN_DEF = 0x2020F6F6
[ 0.347639] imx-ipuv3 2400000.ipu: DMFC_IC_CTRL = 0x00000002
[ 0.347646] imx-ipuv3 2400000.ipu: IPU_FS_PROC_FLOW1 = 0x00000000
[ 0.347653] imx-ipuv3 2400000.ipu: IPU_FS_PROC_FLOW2 = 0x00000000
[ 0.347659] imx-ipuv3 2400000.ipu: IPU_FS_PROC_FLOW3 = 0x00000000
[ 0.347665] imx-ipuv3 2400000.ipu: IPU_FS_DISP_FLOW1 = 0x00000000
[ 0.347672] imx-ipuv3 2400000.ipu: IPU_VDIC_VDI_FSIZE = 0x00000000
[ 0.347678] imx-ipuv3 2400000.ipu: IPU_VDIC_VDI_C = 0x00000000
[ 0.347685] imx-ipuv3 2400000.ipu: IPU_IC_CONF = 0x00000000
[ 0.347693] imx-ipuv3 2400000.ipu: panel size = 800 x 480
[ 0.347699] imx-ipuv3 2400000.ipu: pixel clk = 28160000
[ 0.347760] imx-ipuv3 2400000.ipu: use special clk parent
[ 0.347772] imx-ipuv3 2400000.ipu: round pixel clk:28159999
[ 0.363233] imx-ipuv3 2400000.ipu: div:1
[ 0.363280] imx-ipuv3 2400000.ipu: initializing idma ch 23 @ f01005c0
[ 0.363292] imx-ipuv3 2400000.ipu: initializing idma ch 23 @ f0101140 sub cpmem
[ 0.363314] imx-ipuv3 2400000.ipu: ch 23 word 0 - 00000000 00000000 00000000 E0000000 00077C63
[ 0.363325] imx-ipuv3 2400000.ipu: ch 23 word 1 - 0D0C0000 01A18000 00E3C000 FFF31FC0 00006208
[ 0.363332] imx-ipuv3 2400000.ipu: PFS 0x7,
[ 0.363338] imx-ipuv3 2400000.ipu: BPP 0x0,
[ 0.363345] imx-ipuv3 2400000.ipu: NPB 0xf
[ 0.363351] imx-ipuv3 2400000.ipu: FW 799,
[ 0.363357] imx-ipuv3 2400000.ipu: FH 479,
[ 0.363364] imx-ipuv3 2400000.ipu: EBA0 0x68600000
[ 0.363371] imx-ipuv3 2400000.ipu: EBA1 0x68600000
[ 0.363377] imx-ipuv3 2400000.ipu: Stride 3199
[ 0.363383] imx-ipuv3 2400000.ipu: scan_order 0
[ 0.363389] imx-ipuv3 2400000.ipu: uv_stride 8712
[ 0.363395] imx-ipuv3 2400000.ipu: u_offset 0x0
[ 0.363401] imx-ipuv3 2400000.ipu: v_offset 0x0
[ 0.363407] imx-ipuv3 2400000.ipu: Width0 7+1,
[ 0.363413] imx-ipuv3 2400000.ipu: Width1 7+1,
[ 0.363420] imx-ipuv3 2400000.ipu: Width2 7+1,
[ 0.363425] imx-ipuv3 2400000.ipu: Width3 7+1,
[ 0.363431] imx-ipuv3 2400000.ipu: Offset0 8,
[ 0.363437] imx-ipuv3 2400000.ipu: Offset1 16,
[ 0.363443] imx-ipuv3 2400000.ipu: Offset2 24,
[ 0.363450] imx-ipuv3 2400000.ipu: Offset3 0
[ 0.404966] imx-ipuv3 2400000.ipu: Channel already disabled 10
[ 0.404974] imx-ipuv3 2400000.ipu: Channel already uninitialized 10
[ 0.411240] imx-ipuv3 2800000.ipu: Channel already disabled 9
[ 0.411249] imx-ipuv3 2800000.ipu: Channel already uninitialized 9
[ 0.420949] imx-ipuv3 2800000.ipu: Channel already disabled 10
[ 0.420959] imx-ipuv3 2800000.ipu: Channel already uninitialized 10
[ 4.632691] imx-ipuv3 2400000.ipu: Channel already disabled 10
[ 4.632699] imx-ipuv3 2400000.ipu: Channel already uninitialized 10

 

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‎04-19-2023 04:52 AM
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tgl
Contributor III
P.S. I've also replicated the registers from Linux (mxc_ccm-CCGR3,mxc_ccm->cs2cdr,mxc_ccm->chsccdr, iomux->gpr[2] = 0x020E0008) the issue is still there. Tampering with them while the display is on, iomux->gpr[2] seems to be the only one that makes any difference, but it's probably because it sets the channel to 18bit, the colors become greyish.
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