openocd imx8 coresight address help

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openocd imx8 coresight address help

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fatalfeel
Contributor V

refer to

imx7 openocd tapid and debug base help

i.mx8 questions

1. whats address of CoreSight Debug Access Port   DAP

2.whats address Base addresses of cores

3. do imx8 have Secure JTAG Controller address? if yes what is it?

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fatalfeel
Contributor V

here support cortex a53 armv8 

Programming Guide: OpenOCD + Eclipse + Jtag debug on Uboot & Linux 

download openocd-0.10.0_v14.tar.gz  you can find imx8.cfg
./configure --prefix=/opt/openocd --enable-maintainer-mode --enable-ftdi --enable-target64

now just waiting CoreSight Debug Access Port    address

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fatalfeel
Contributor V

Programming Guide: Jtag Openocd Eclipse debug 

put

openocd-0.10.1_v01.tar 

imx8-ngb.cfg imx8m-ngb.cfg all test pass

include core m4

//connect succesful message

root@ublinux:~# openocd -f /opt/openocd/share/openocd/scripts/target/imx8m-ngb.cfg
Open On-Chip Debugger 0.10.0+dev
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
Info : If you need SWD support, flash KT-Link buffer from https://github.com/bharrisau/busblaster
and use dp_busblaster_kt-link.cfg instead
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
clear_regs
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : clock speed 1000 kHz
Info : JTAG tap: imx8m.cpu tap/device found: 0x5ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x5)
Info : imx8m.cpu.0: hardware has 6 breakpoints, 4 watchpoints
Info : Listening on port 3333 for gdb connections
Info : Listening on port 3334 for gdb connections

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fatalfeel
Contributor V

here support cortex a53 armv8 

Programming Guide: OpenOCD + Eclipse + Jtag debug on Uboot & Linux 

download openocd-0.10.0_v14.tar.gz  you can find imx8.cfg
./configure --prefix=/opt/openocd --enable-maintainer-mode --enable-ftdi --enable-target64

now just waiting CoreSight Debug Access Port    address

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fatalfeel
Contributor V

I found them in http://fatalfeel.blogspot.tw/2015/12/openocd-with-eclipse-debug-kernel-of.html

in imx8.cfg


# Freescale i.MX8 series single/dual/quad core processor

if { [info exists CHIPNAME] } {
   set  _CHIPNAME $CHIPNAME
} else {
   set  _CHIPNAME imx8
}

# Debug Access Port
if { [info exists DAP_TAPID] } {
        set _DAP_TAPID $DAP_TAPID
} else {
        set _DAP_TAPID 0x5ba00477
}

jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
        -expected-id $_DAP_TAPID

# SDMA / no IDCODE
#jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f

# SOC JTAG ID / IDCODE refer to BSDL file
#if { [info exists SJC_TAPID] } {
#        set _SJC_TAPID $SJC_TAPID
#} else {
#        set _SJC_TAPID 0x1cf80553
#}
#set _SJC_TAPID1 0x2cf80553

#jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
        -expected-id $_SJC_TAPID -expected-id $_SJC_TAPID1

# GDB target: Cortex-A53, using DAP, configuring only one core
# Coresight base address:
# core 0  -  0x80410000 / cti - 0x80420000
# core 1  -  0x80510000 / cti - 0x80520000
# core 2  -  0x80610000 / cti - 0x80620000
# core 3  -  0x80710000 / cti - 0x80720000
set _TARGETNAME $_CHIPNAME.cpu0
#set _TARGETNAME_1 $_CHIPNAME.cpu1
#set _TARGETNAME_2 $_CHIPNAME.cpu2
#set _TARGETNAME_3 $_CHIPNAME.cpu3

target create $_TARGETNAME aarch64 -chain-position $_CHIPNAME.dap -coreid 0 -dbgbase 0x80410000 -ctibase 0x80420000
#target create $_TARGETNAME_1 aarch64 -chain-position $_CHIPNAME.dap -coreid 1 -dbgbase 0x80510000 -ctibase 0x80520000
#target create $_TARGETNAME_2 aarch64 -chain-position $_CHIPNAME.dap -coreid 2 -dbgbase 0x80610000 -ctibase 0x80620000
#target create $_TARGETNAME_3 aarch64 -chain-position $_CHIPNAME.dap -coreid 3 -dbgbase 0x80710000 -ctibase 0x80720000
        
# some TCK cycles are required to activate the DEBUG power domain
#jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"

proc imx8_dbginit {target} {
        # General Cortex-A53 debug initialisation
        aarch64 dbginit
}

# Slow speed to be sure it will work
adapter_khz 1000
$_TARGETNAME configure -event reset-start { adapter_khz 1000 }

$_TARGETNAME configure -event reset-assert-post "imx8_dbginit $_TARGETNAME"
$_TARGETNAME configure -event gdb-attach { halt }

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sinanakman
Senior Contributor III

Hi Jesse

If i.mx8 implemented the ROM table properly "dap info" might show the component

and the debug base address. Create the tap first and run  dap info <tap_number> .

Hope this helps

Regards

Sinan Akman

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b36401
NXP Employee
NXP Employee

We have no such detailed document for i.MX8 as you refered for i.MX7.
Please wait a bit.

Have a great day,
Victor

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fatalfeel
Contributor V

have the answer now?

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