Hi, nxp
We find problems during product development and leave inquiries.
The ap I use is s32v232. This ap supports up to emmc 4.41.
In emmc ddr52 mode, the bus width max is known to be 104MB/s. But the results of our testing are as follows:
//////////////////////////////////////////////////////////////////////////////////////////////////////////////
/ # hdparm -t /dev/mmcblk0
/dev/mmcblk0:
Timing buffered disk reads: 85 MB in 3.03 seconds = 28715 kB/s
/ # [ 196.353005] random: crng init done
//////////////////////////////////////////////////////////////////////////////////////////////////////////////
/ # dd if=/testfile of=/dev/mmcblk0p3 bs=1M count=300
300+0 records in
300+0 records out
314572800 bytes (300.0MB) copied, 11.514134 seconds, 26.1MB/s
/ #
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As above, the read/write performance of emmc is only 26~28MB.
I don't think this is a matter of emmc performance. Because, emmc supports 280MB to read in hs400 mode.
So we are thinking that there is a problem with the AP's emmc controller.
I don't know how to attach the photo, so I leave a link.
In the link, I captured the waveform of emmc.
Red : cmd
Yellow: clock
Blue : data0
If you look closely at the clock part, you can see that it operates at 52mhz and then at a slower speed. This occurs periodically, and an interver occurs every two clocks.
The reason for the slow read/write performance is a situation where there is a suspected problem with the clock control.
Please review whether there is a problem with the waveform.
And what should we expect of emmc's max performance in s32v232 ap?
