I was looking at an issue with our board driving our parallel LCD and noticed a couple of things:
1) the speed and drive strength fields of registers like IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK are documented differently in the i.MX6 Solo reference manual and the i.MX6 Quad reference manual.
For example for the Solo SPEED field it says
00 RESERVED0 — Reserved
01 50MHZ — Low (50 MHz)
10 100MHZ — Medium (100 MHz)
11 200MHZ — Maximum (200 MHz
for the Quad it says:
00 LOW — Low frequency (50 MHz)
01 MEDIUM — Medium frequency (100, 150 MHz)
10 MEDIUM — Medium frequency (100, 150 MHz)
11 MAXIMUM — Maximum frequency (100, 150, 200 MHz)
Is this something that got revised only in the Quad manual? Are they really different?
2) the device tree files for the 3.10.17 kernel set most of the LCD IO to use a value of 0x10 for the IOMIXC PAD_CTL registers. Depending on which reference manual you read this is either an invalid value or this is a 75Ohm/3.3V driver and low speed. This seems like a very low drive, especially for the clock. I realize this is very board and LCD dependent, but I would suggest it would be good policy to put a note in the .dtsi file marking this as something that needs attention.
