ksz8863 port2 becaming ready signal was ignored

cancel
Showing results for 
Search instead for 
Did you mean: 

ksz8863 port2 becaming ready signal was ignored

Jump to solution
834 Views
tootzoe
Contributor III

Hi all, 

I'am integrating ksz8863  to our customer board, based on  yocto linux-4.1.15-2.0.1 , 

now the fec is working correctly on linux, 3 ports work well  on RMII mode,  ( on u-boot-2016.03 alsa worked with port1 ),

 the only issues is that port2 (switch port) of ksz8863 is unable to notification imx6dl the network is became ready.

we must plugin cable to port1 of ksz8863 to activity the fec(ksz8863) , then 3 ports do data communication well,

ksz8863 port2 is able to notify imx6 that network is ready, because we have mx53 platform based on linux-2.6  that achieve this funciton, on mx53 platform, both ports of ksz8863 can notify CPU and to activity PHY 0:1 fec

it seems data report from port2(i guess have diffreenct id  ) to imx6dl is ignored....

 

is there somebody who know how to fix this?

Thanks in advance!!

Best regards!

toot_hzf

Labels (3)
0 Kudos
1 Solution
274 Views
tootzoe
Contributor III

i believed  there is a easy way to achieve this functionality, by setting the ksz8863's registers correctly,

But,  i can't find how to modify the registers inside ksz8863, so, 

I am now using a not so clever method solved this problem.

for port1 and port2 of ksz8863 is connected as switch,  so i check port2 phydev link status, once port2 is link up, i set the force_lnk bit( reg 0x1F , bit3) of port1's phydev,  when port2 link down, clear this bit, this method works for my project, i prefer to find a better way is i have free time....

toot_hzf

View solution in original post

0 Kudos
3 Replies
274 Views
igorpadykov
NXP TechSupport
NXP TechSupport

Hi

this chip is not supported in nxp bsp releases and one can also post

it  on meta-fsl-arm mailing list, so that more people could try to assist you.
https://lists.yoctoproject.org/listinfo/meta-freescale

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 Kudos
274 Views
tootzoe
Contributor III

hi igor, 

thanks for replying , i try to fix this myself , i'v got the mx53 kernel source code, hope not so much difficult ....

Best regards!

toot_hzf

0 Kudos
275 Views
tootzoe
Contributor III

i believed  there is a easy way to achieve this functionality, by setting the ksz8863's registers correctly,

But,  i can't find how to modify the registers inside ksz8863, so, 

I am now using a not so clever method solved this problem.

for port1 and port2 of ksz8863 is connected as switch,  so i check port2 phydev link status, once port2 is link up, i set the force_lnk bit( reg 0x1F , bit3) of port1's phydev,  when port2 link down, clear this bit, this method works for my project, i prefer to find a better way is i have free time....

toot_hzf

View solution in original post

0 Kudos