Hi all,
We have a customized imx8mn board that uses ksz8081 as an ethernet PHY chip.
We can successfully probe the PHY chip with the following kernel print:
Micrel KSZ8081 or KSZ8091 30be0000.ethernet-1:02: attached PHY driver [Micrel KSZ8081 or KSZ8091] (mii_bus:phy_addr=30be0000.ethernet-1:02, irq=77)
However, there is no auto-detected like "ADDRCONF(NETDEV_UP): eth0: link is not ready/link becomes ready" when cable plug-in.
Following is the schematic of phy connection:
I have two questions :
1. Here we just pull high the RST pin of ksz8081. Is that correct? Here we think the PHY chip will get rested when power on according to mircon datasheet. Although, we find most people controlled this pin with gpio.
2. Is that correct to use MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK and do we need any modification of the clock source inside the device tree, like using PLL2_50M? (since here I see someone are using an external oscillator).
3. Is there any other place not properly implemented?
following is the device tree we used:
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f /* ref_clk */
MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x1f
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x91
MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER 0X1f
>;
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rmii";
phy-handle = <ðphy0>;
//phy-reset-gpios = <&pca9450 0 GPIO_ACTIVE_LOW>;
//phy-reset-duration = <10>;
//phy-reset-post-delay = <150>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
};
};
};
fec1: ethernet@30be0000 {
compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
reg = <0x30be0000 0x10000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,
<&clk IMX8MN_CLK_ENET1_ROOT>,
<&clk IMX8MN_CLK_ENET_TIMER>,
<&clk IMX8MN_CLK_ENET_REF>,
<&clk IMX8MN_CLK_ENET_PHY_REF>;
clock-names = "ipg", "ahb", "ptp",
"enet_clk_ref", "enet_out";
assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
<&clk IMX8MN_CLK_ENET_TIMER>,
<&clk IMX8MN_CLK_ENET_REF>,
<&clk IMX8MN_CLK_ENET_TIMER>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
<&clk IMX8MN_SYS_PLL2_100M>,
<&clk IMX8MN_SYS_PLL2_125M>;
assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
stop-mode = <&gpr 0x10 3>;
fsl,wakeup_irq = <2>;
status = "disabled";
};
Thanks for your help.
