imx8qm Interrupt Handling for Cortex M4 core

[sohaib_sulehri]

Hi,

I am trying to understand the interrupt routing to Cortex M4_0 core and how interrupt priorities are handled.

My current understanding is that Cortex M4 subsystem has two level of interrupts.
Level 1 (IRQn 0 to 51) are local to Cortex M4 subsystem and they are 1:1 mapped to NVIC channels.
Level 2 are external to Cortex M4 subsystem and they not 1:1 mapped to NVIC channel. Instead the are divided into 8 groups, 64 interrupts each group and are mapped to 8 NVIC channels i.e. IRQn 32 to IRQn 39. That means that external interrupts like AUDIO_GPT0 and AUDIO_GPT1 will be mapped to same NVIC IRQn 38. If my understanding is correct then I have following questions.

Q1: Is there still a way we can route AUDIO_GPT0 and AUDIO_GPT1 to different NVIC channel?    
Q2: Can I have different interrupt priority levels for AUDIO_GPT0 and AUDIO_GPT1?

We have to support AUTOSAR OS on Cortex M4 core. AUTOSAR OS has different priorities for CATEGORY 1 and CATEGORY 2 interrupts. 

Q3: If answer to Q1 and Q2 is 'NO' then how can I use AUDIO_GPT0 as CATEGORY 1 and AUDIO_GPT1 as CATEGORY 2 at the same time? I am asking this to check if you have seen such a use case before and if you have a workaround for this.

Thanks

[jimmychan · Accepted solution]

Unfortunately AUDIO_GPT0 and AUDIO_GPT1 cannot be set with different priorities. These interrupts are grouped into one interrupt steer and then this interrupt steer is routed to NVIC IRQ 38. The interrupt priorities are controlled by NVIC - for NVIC interrupts are one IRQ.