Said CPU use same USB IP. A question regarding the USB3 glue registers: For i.MX8MP there is USB_CTL1, which enables to select PWR and OC polarity. This register is not documented in i.MX8MQ reference manual. Is this register not implemented in silicon or is the manual wrong?
Background: most protection cirquits for USB Overcurrent have a low active output signal. i.MX8MP manual describes this input as high active by default (like the older i.MX CPU)
