Hi,
I have a custom board (and a solidrun EVB with the same behavior) which has TI's eDP bridge sn65dsi86.
when using a refclk the bridge/display works fine but when providing it with the mipi_dsi clocks (after disconnecting the ext clk) it fails with edp errors:
[ 6.570668] ti_sn65dsi86 1-002c: [drm:ti_sn_bridge_enable [ti_sn65dsi86]] *ERROR* Can't read lane count (-110); assuming 4
[ 7.092286] ti_sn65dsi86 1-002c: [drm:ti_sn_bridge_enable [ti_sn65dsi86]] *ERROR* Can't read eDP rev (-110), assuming 1.1
[ 7.432894] ti_sn65dsi86 1-002c: [drm:ti_sn_bridge_enable [ti_sn65dsi86]] *ERROR* Can't read max rate (-110); assuming 5.4 GHz
[ 7.765867] ti_sn65dsi86 1-002c: [drm:ti_sn_bridge_enable [ti_sn65dsi86]] *ERROR* Link training failed, link is off (-5)
when the bridge module loads i can see the dsi clock goes up and down once and then stops.
I'm working on kernel 5.15 (also tried 5.10 on solidruns EVB). these are the dts nodes:
sn65dsi86: sn65dsi86@2d {
...
clocks = <&mipi_dsi 0>,
<&clk IMX8MP_VIDEO_PLL1_OUT>;
clock-names = "mipi_clk", "video_pll";
...
}
mipi_dsi: mipi_dsi@32e60000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-mipi-dsim";
#clock-cells = <1>;
reg = <0x32e60000 0x10000>;
clocks = <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_DSI_PCLK>,
<&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_DSI_CLKREF>;
clock-names = "cfg", "pll-ref";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
assigned-clock-rates = <12000000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&mipi_phy1_pd>;
status = "disabled";
port@0 {
dsim_from_lcdif: endpoint {
remote-endpoint = <&lcdif_to_dsim>;
};
};
};
I tried various clocks (like IMX8MP_VIDEO_PLL1_OUT) and also to re-parent the dsi from IMX8MP_CLK_24M (which fails on dtc compilation).
would appreciate any help,
thanks!
HI,
can you please elaborate on the formula, its parameters and how should the output value be used?
I've used the same clock in my bridge' node:
clocks = <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
clock-names = "pll-ref";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
assigned-clock-rates = <12000000>;
Have you solved this problem? I am also encountering this problem with IMX8MM.
when using a refclk the bridge/display works fine but when providing it with the mipi_dsi clocks (after disconnecting the ext clk) it fails with edp error
>why do you change the refclk to the mipi dsi clocks? pls provide you full dts file to check