imx6sx MCC memory location

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 
已解决

imx6sx MCC memory location

跳至解决方案
2,383 次查看
tcmichals
Contributor III

The Linux driver for mcc and M4 linker files use 0xBFF00000 memory address. DDR RAM starts at 0x80000000 and goes to 512M or 1G. 1G(0x3f800000) + 0x8000_0000 is  0xBF800000, According to manual section 2.2 IMX 6SX 8000_0000 to FFFF_FFFF is the MMDC xDDR controller.

- what is the type of memory is being referenced, i.e SRAM, DDR. (the linker files states its DDR) some other mapping?

- is there a Linux driver that creates this mapping?

标签 (3)
0 项奖励
1 解答
1,357 次查看
tcmichals
Contributor III

OK.. But it does not go into detail about how the address is setup fro the shared RAM... I've two RAM layouts shown below:

BFF00000 is defined as MCC_BASE_ADDRESS in mcc_config_linux.h

1GB

physical memory      80000000 +

1GB of RAM             40000000 =

top address is           C0000000 - BFF00000 = 100000  1MB of RAM

512MB

9ff00000 is defined as MCC_BASE_ADDRESS in mcc_config_linux.h

80000000 + 20000000 = A0000000 - 9ff00000 = 100000

But this does not work.. mcc_get_bookeeping_data crashes using ioremap_nocache

Or I'm not understanding the memory mapping of DDR memory to MCC_BASE_ADDRESS?

在原帖中查看解决方案

0 项奖励
5 回复数
1,357 次查看
renfeiche
Contributor I

I have the same question! I don't know how to define the MCC_BASE_ADDRESS, and the mcc_get_bookeeping_data() always return null. Could you tell me do you have the answer?

Best Regards!

0 项奖励
1,357 次查看
niranjanbc
Contributor IV

Hi I have same problem, were you able to get the solution for your issue.

0 项奖励
1,357 次查看
niranjanbc
Contributor IV

 i got the problem fixed by adding the linux memory usage into dts file.

{
    memory {
        linux,usable-memory = <0x80000000 0x3ff00000>;
        reg = <0x80000000 0x40000000>;
    };
};

0 项奖励
1,357 次查看
igorpadykov
NXP Employee
NXP Employee

Hi Tim

for mapping one can look linux../../arm/mach-imx/hardware.h

mcc driver is described in attached Linux Manual

Chapter 53 i.MX 6 SoloX Multi-Core Communication (MCC)

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

0 项奖励
1,358 次查看
tcmichals
Contributor III

OK.. But it does not go into detail about how the address is setup fro the shared RAM... I've two RAM layouts shown below:

BFF00000 is defined as MCC_BASE_ADDRESS in mcc_config_linux.h

1GB

physical memory      80000000 +

1GB of RAM             40000000 =

top address is           C0000000 - BFF00000 = 100000  1MB of RAM

512MB

9ff00000 is defined as MCC_BASE_ADDRESS in mcc_config_linux.h

80000000 + 20000000 = A0000000 - 9ff00000 = 100000

But this does not work.. mcc_get_bookeeping_data crashes using ioremap_nocache

Or I'm not understanding the memory mapping of DDR memory to MCC_BASE_ADDRESS?

0 项奖励