imx6s ENET EIMR register setting

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imx6s ENET EIMR register setting

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hailiu
Contributor IV

Dear friends,

Right now I am debugging ENET Module using KSZ9201 Phy. Now I can communicate with KSZ9201 and read ID's and all the registers.I can also see the 125MHz clock feed to MAC, and the 125MHz clock comes out of MAC from RXC pin.  I am trying to do a digital loopback to test other functionality. Right now, only GRA interrupt occured, I guess the setting may not be correct. I checked the SDK code and found that the EIMR register is set to 0. Accourding to RM, to enable an interrupt to occure, the corresponding EIMR bit should be set to 1, why SDK code set it to 0?  Is it need to be set to 0 for an interrupt to occur?

thank you,

Hai 

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igorpadykov
NXP Employee
NXP Employee

Hi Hai

 

one can check it in linux fec_main.c ethernet driver, pay attention to line

1132 /* Enable interrupts we wish to service */    :

https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/net/ethernet/freescale/fec_main.c?...

 

Best regards
igor

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