imx6 Clock Problem

[deepanrajanbara]

Hi Sir,

Ours is a custom board based on imx6 .we wanted to change to clock of clko to 48Mhz by default it is 24Mhz and uses clko2 as parent.But when we try to change the parent clock of clko2 it changes but when trying to change the clko we are not able to change s there is possible way to set the clock of clko as 48Mhz in arch/arm/mach-mx6/clock.c. I have tried a lot of procedure to change clock in board_init() and clock.c nothing seems to take effect.Can any one help me please.

Thank you,

Deepanraj.A

[igorpadykov]

Hi Deepanraj

you can try to output with CCM_CCOSR setting:

CLKO1_SEL=0000 pll3_sw_clk (this inputs has additional constant division /2)

CLKO1_DIV=100 divide by 5

(I believe in linux pll3_sw_clk = 480000000)

and this should result in 480000000/2/5=48 Mhz

Best regards

igor

[deepanrajanbara]

Hi Igor,

But Actually i am not sure of where to put the divider if it crossed 10 it rounded to 8 so am getting some other value.and how to enable clko1_sel in clock.c am not sure can u help me am new to this.

Thank you,

Deepanraj.A

[igorpadykov]

you should use divide by 5

CLKO1_SEL=0000 pll3_sw_clk (this inputs has additional constant division /2)

CLKO1_DIV=100 divide by 5

[deepanrajanbara]

Hi Igor,

But i don't know where to set divide by 5 ? :smileysad:

Can get more detail on where to set and how to Configure...?

Thank you,

Deepanraj.A

[igorpadykov]

Hi Deepanraj

I would suggest to try SDK running it with jtag

i.MX 6Series Platform SDK : Bare-metal SDK

Best regards

igor

[deepanrajanbara]

Hi Igor

We are not using JTAG.Is there anyway to check the clock without using JTAG ?

Thank you,

Deepanraj.A

[igorpadykov]

you can run it with SD.

Read documentation inside SDK.

Best regards

igor

[igorpadykov]

Hi Deepanraj

BSP version L3.0.35_4.1.0_130816 .

The location of the file is

/arch/arm/mach-mx6/clock.c

you can add codes to function _clk_clko_set_rate() in clock.c,

__raw_writel(dividerbyN, MXC_CCM_CCOSR);

one can check CCM_CCOSR sect.18.6.21 CCM Clock Output Source Register

(CCM_CCOSR) IMX6DQRM

~igor

[deepanrajanbara]

Hi Igor

If i set the dividerbyN as 5. i am getting 96Mhz but actually the clock has internal constant divider of 2.

Thankyou,

Deepanraj.A

[igorpadykov]

PLL3 is dedicated USB PLL, 480MHz.

So dividing it by 10 one should get 48MHz

[deepanrajanbara]

Hi Igor,

Divide by 10 is this possible in reference manual  the  divider is only from 1-8.As mentioned PLL3 (this inputs has additional constant division /2) and when i divide by 5 so totally 10 i should get 48Mhz.But i am not able to achieve 48Mhz.:smileysad:

Thank you,

Deepanraj.A

[deepanrajanbara]

Hi Igor

Thank you for you support.

Deepanraj.A