Hi,
I have a follow up question regarding this topic
https://community.nxp.com/t5/i-MX-RT/imx-rt-1024-internal-flash-configure-as-RWW/td-p/1584737
So we are using a part of flash as "eeprom" and we learned in previous question that we must run code in SRAM while operating flash (read/write/erase). Since we also run free rtos, we can have task switches while an operation in flash is pending. I think we'll run into hard faults when free rtos switches to a task executes code which runs from flash while for example we were busy with writing to flash.
Therefore, I put all "flash operations" (read/write/erase) in critical sections, so that I can guarantee that these actions are completely finished before allowing freertos to task switch.
This, is very annoying, because when a sector erase needs to be performed, free rtos will be "effectively dead" until the sector erase is done. During that time, my software is unable to respond to interrupts. Well, not all of them, some interrupts I also run in ITC sram (e.g. my RTC clock and some timers), but most of the application is temporary unresponsive due to these critical sections I set around the flash operation routines.
So my question is, do I *need* to do this? I think I am asking what the flash timing are. Lets say task 1 is active, and it needs to erase a sector on flash. What if I don't put a critical section around it, and allow free rtos to preempt the task, and "while flash is erasing a sector" freertos orchestrates a task switch (which already executes from flash). I guess this would hard fault? Is that correct? Are there alternatives possible that would prevent this hard fault, other then protecting the entire sector erase call with a critical section?
I hope you understand my somewhat poorly formulated question.
