I am trying to understand how FLEXSPI gets configured for a 1024. I know the ROM code is responsible for setting it up without DQS, and does some magic that sets the flexspi clocks, and that startup code nor polling SDK example reinitializes flexspi at 133 MHz.
I know the macros XIP_EXTERNAL_FLASH and XIP_BOOT_HEADER_DCD_ENABLE having influence on this flexspi configuration, but I am completely lost on what EXACTLY happens WHERE and WHY.
Then this comment struck me:
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
Can you confirm that the clock source for flexspi is usb1, and thus, that changes to PFD2 clock as done here have no impact at all??
static inline void flexspi_clock_init()
{
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
/* Switch to PLL2 for XIP to avoid hardfault during re-initialize clock. */
CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); /* Set PLL2 PFD2 clock 396MHZ. */
CLOCK_SetMux(kCLOCK_FlexspiMux, 0x2); /* Choose PLL2 PFD2 clock as flexspi source clock. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2); /* flexspi clock 133M. */
#else
const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U};
CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll);
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 24); /* Set PLL3 PFD0 clock 360MHZ. */
CLOCK_SetMux(kCLOCK_FlexspiMux, 0x3); /* Choose PLL3 PFD0 clock as flexspi source clock. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2); /* flexspi clock 120M. */
#endif
}
Is there any application note that explains the FLEXPI mystery properly? I am going back and forth between reference manual, SDK examples, and mystic comments. I really hope there is somebody at NXP support who still understands how all of this works.
