Hi,
I'm currently working on a baremetal application on the M4 inside the i.MX8QXP and I'm having issues activating the cache. I would like to make sure I'm not missing any steps. I based my configuration of the MPU and cache on the configuration found in FreeRTOS_BSP_1.0.1_IMX7D. The application code and data are in DDR at 0x8000_0000. Here are the configuration steps:
Is there any steps that I'm missing to enable the cache properly ? If you need any more information please feel free to ask.
Thanks for your support,
David
Hello,
Use the SDK as code examples.
Welcome | MCUXpresso SDK Builder
https://mcuxpresso.nxp.com/en/select
Regards,
Yuri.
Hi,
Will IMx8QxP support the Baremetal application? If it supports please share the document of the IMX8QxP Baremetal user guide or any other reference document.
Regards & Thank You,
Saravanan Shanmugam
Hi Yuri,
Thanks for the quick response. I had an issue in the initialisation of the LMEM controller. I still have a few questions about the overall operation of the M4.
From the reference manual it is explicitly mentioned that the code cache is both an instruction and data cache.
Thanks for your support, I really appreciate it
David
Hello,
Please look at my comments below.
Based on i.MX8X RM (IMX8DQXPRM, Rev. 0, 05/2020):
Low-order addresses (0x0000_0000 - 0x1FFF_FFFF) use the Processor Code (PC) bus,
and high-order addresses (0x2000_0000 - 0xFFFF_FFFF) use the Processor System (PS) bus.
Normal operation has code accesses on the PC bus and data accesses on the PS bus.
Chapter 2 (Memory Map) of the RM provides information, what devices / addresses
can be accessed via PC and PS buses. All accesses, that are not mapped to corresponding
TCM are intended for the cache controllers:
Processor Code accesses are routed to the SRAM_L if they are mapped to that space.
All other PC accesses are routed to the Code Cache Memory Controller. This controller
then processes the cacheable accesses as needed, while bypassing the non-cacheable, cache
write-through, cache miss ...
Processor Space accesses are routed to the SRAM_U if they are mapped to that space.
All other PS accesses are routed to the PS Cache Memory Controller. This controller then
processes the cacheable accesses as needed, while bypassing the non-cacheable, cache
write-through, cache miss ...
To enable / disable the caches LMEM_PCCCR[ENCACHE] and / or LMEM_PSCCR[ENCACHE]
should be set / cleared.
Regards,
Yuri.