iMX8MP FEC RMII reference clock (50MHz) in u-Boot

[khang_letruong]

Dear Community,

I am bringing up the LAN8720Ai PHY in an iMX8MP based custom board and I would like to have 50MHz frequency fed to the PHY by the MAC which is the SoC. Below is the relevant setting of the board:

<uboot-imx>/configs/toto_imx8mp_defconfig :

CONFIG_PHY_SMSC=y
CONFIG_PHYLIB=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
# CONFIG_DWC_ETH_QOS is not set
# CONFIG_DWC_ETH_QOS_IMX is not set
CONFIG_FEC_MXC=y
CONFIG_MII=y

<uboot-imx>/include/configs/toto_imx8mp.h :

/* ENET Config */
/* ENET1 */

#if defined(CONFIG_CMD_NET)
#define CONFIG_ETHPRIME                 "eth0" /* Set fec to primary since we use its MDIO */

#define CONFIG_FEC_XCV_TYPE             RMII // 100 Base-tx reduced pin count interface
#define CONFIG_FEC_MXC_PHYADDR          0 // Only FEC is used, QOS is disabled

#define DWC_NET_PHYADDR                 1

#define PHY_ANEG_TIMEOUT 20000

#endif

<uboot-imx>/arch/arm/dts/imx8mp-toto.dts :

&fec {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_fec>;
        phy-mode = "rmii";
        phy-handle = <&ethphy1>;
        status = "okay";

        mdio {
                #address-cells = <1>;
                #size-cells = <0>;

                ethphy1: ethernet-phy@1 {
                        compatible = "ethernet-phy-ieee802.3-c22";
                        reg = <1>;
                        max-speed = <100>;
                        reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
                        reset-delay-us = <1000>;
                        reset-post-delay-us = <1000>;
                };
        };
};

        ...

        pinctrl_fec: fecgrp {
                fsl,pins = <
                        MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC               0x3
                        MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO              0x3
                        MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0         0x91
                        MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1         0x91
                        MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL      0x91
                        MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0         0x1f
                        MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1         0x1f
                        MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL      0x1f
                        MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER             0x1f
                        MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02              0x19
                        MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK            0x4000001f
                >;
        };

As I used SAI1_MCLK for generating the clock, I temporary updated the following iomuxc setting of USB type C:

        pinctrl_typec_mux: typec1muxgrp {
                fsl,pins = <
//                      MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20      0x16
                        MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21      0x16
                >;
        };

and the switch-gpios property of  cbtl04gp node in <uboot-imx>/arch/arm/dts/imx8mp-toto-som.dtsi (included in <uboot-imx>/arch/arm/dts/imx8mp-toto.dts) accordingly :

/ {
        ...
        cbtl04gp {
                compatible = "nxp,cbtl04gp";
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_typec_mux>;
                switch-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
                orientation-switch;

                port {
                        usb3_data_ss: endpoint {
                                remote-endpoint = <&typec_con_ss>;
                        };
                };
        };
};

Note : I did not want to modify much the USB interfaces in the device-trees and that was the reason I replaced GPIO4_IO20 by GPIO4_IO21.

Next, I followed the instruction in the community to enable the 50MHz reference clock on  MX8MP_IOMUXC_SAI1_MCLK__ENE... pin :

a.  <uboot-imx>/board/<company>/toto_imx8mp/toto_imx8mp.c:

#define FEC_RST_PAD IMX_GPIO_NR(4, 2)
static const iomux_v3_cfg_t fec1_rst_pads[] = {
        MX8MP_PAD_SAI1_RXD0__GPIO4_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
};

static void setup_iomux_fec(void)
{
        imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
                                         ARRAY_SIZE(fec1_rst_pads));

        gpio_request(FEC_RST_PAD, "fec1_rst");
        gpio_direction_output(FEC_RST_PAD, 0);
        mdelay(15);
        gpio_direction_output(FEC_RST_PAD, 1);
        mdelay(100);
}

static int setup_fec(void)
{
        struct iomuxc_gpr_base_regs *gpr =
                (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;

        setup_iomux_fec();

        /* Enable RMII TX clk output */
        setbits_le32(&gpr->gpr[1], IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);

        return set_clk_enet(ENET_50MHZ);
}

b. Add 50MHz frequency into the end of assigned-clock-rates property of the fec node in  <uboot-imx>/arch/arm/dts/imx8mp-toto-som.dtsi:

&fec {
        assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
                          <&clk IMX8MP_CLK_ENET_TIMER>,
                          <&clk IMX8MP_CLK_ENET_REF>,
                          <&clk IMX8MP_CLK_ENET_PHY_REF>;
        assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
                                 <&clk IMX8MP_SYS_PLL2_100M>,
                                 <&clk IMX8MP_SYS_PLL2_50M>,
                                 <&clk IMX8MP_SYS_PLL2_50M>;
        assigned-clock-rates = <0>, <100000000>,
                               <50000000>, <50000000>;
};

But I could not see any waveform when probing on the GPIO4_IO20 (SAI1_MCLK/ENET1_TX_CLK) pin. Could you help to point out the missing piece of the configuration, please ?

Thanks in advance and best regards,

Khang

[khang_letruong · Accepted solution]

Hi again,

The instruction in https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX8MM-RMII-TXC-OUTPUT/ta-p/1476812 resolved my issue.

Best regards,

Khang