How MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK generator 50MHz clock to ENET_PHY_REF

[benyoung]

Hi Currently I need to bring up FEC with RMII mode on iMX8MP, but the ENET_PHY_REF can't measure 50MHz clock input, below is my dts setting:

&fec {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_fec>;
    clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
                  <&clk IMX8MP_CLK_SIM_ENET_ROOT>,
                  <&clk IMX8MP_CLK_ENET_TIMER>,
                  <&clk IMX8MP_CLK_ENET_REF>,
                  <&clk IMX8MP_CLK_ENET_PHY_REF>;
    clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out";
    assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
                  <&clk IMX8MP_CLK_ENET_TIMER>,
                  <&clk IMX8MP_CLK_ENET_REF>,
                  <&clk IMX8MP_CLK_ENET_PHY_REF>;
    assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
                  <&clk IMX8MP_SYS_PLL2_100M>,
                  <&clk IMX8MP_SYS_PLL2_50M>,
                  <&clk IMX8MP_SYS_PLL2_50M>;
    assigned-clock-rates = <0>, <100000000>, <50000000>,<50000000>;
    phy-mode = "rmii";
    phy-handle = <&ethphy1>;
    phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
    phy-reset-duration = <10>;
    //fsl,magic-packet;
    status = "okay";

    mdio {
              #address-cells = <1>;
              #size-cells = <0>;

              ethphy1: ethernet-phy@4 {
                  compatible = "ethernet-phy-ieee802.3-c22";
                  reg = <4>;
                  max-speed = <100>;
                  eee-broken-1000t;
              };
　　};
};

pinctrl_fec: fecgrp {
　　fsl,pins = <
　　　　MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x1c4 //RMII IRQ
　　　　MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
　　　　MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
　　　　MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
　　　　MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
　　　　MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
　　　　MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
　　　　MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
　　　　MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
　　　　MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19 //RMII Reset
　　　　MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x4000001f
　　>;
};

Can any one provide a suggestion? Thanks!

[benyoung]

By your suggestion, I modify some statements as below shown, it works

static int setup_fec(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;

setup_iomux_fec();

/* Enable RGMII TX clk output */
setbits_le32(&gpr->gpr[1], BIT(13));

return set_clk_enet(ENET_50MHZ);

}

But another question, can it move to kernel level and do the same purpose?

[igorpadykov]

Hi young

enet clock direction can be configured using IOMUX GPR1 register in uboot setup_iomux_fec() function

https://source.codeaurora.org/external/imx/uboot-imx/tree/board/freescale/imx8mp_evk/imx8mp_evk.c?h=...

Best regards
igor

[benyoung]

By your suggestion, I modify some statements as below shown, it works

static int setup_fec(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;

setup_iomux_fec();

/* Enable RGMII TX clk output */
setbits_le32(&gpr->gpr[1], BIT(13));

return set_clk_enet(ENET_50MHZ);

}

But another question, can it move to kernel level and do the same purpose?

[benyoung]

After we got the 50MHz clock from ENET1_TX_CLK, but we measure the RMII TX/RX communication, still got nothing. Can you provide suggestion? Could you help to confirm my dts with RMII mode  design ?

[khang_letruong]

Hi @benyoung ,

How did you obtain 50MHz refclock on MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK in kernel, please ? I am struggling with similar issue described here : https://community.nxp.com/t5/i-MX-Processors/IMX8MM-RMII-mode-50MHz-output-disappears-during-kernel-...

Best regards,

Khang