iMX8MM, problems on early I2C access from SPL

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iMX8MM, problems on early I2C access from SPL

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dzim
Contributor I

We are developing a custom board based on iMX8MMDL.
The PMIC for the SoC is connected to I2C4.
We need to access the PMIC early while running the SPL to tune voltages.

Unfortunately we fail to do so, the probing of the PMIC does not work, giving this error message (repeatedly because of retries):

wait_for_sr_state: failed sr=81 cr=a0 state=2020


According to the sources the message should originate from mxc_i2c.c , i2c_init_transfer:

wait_for_sr_state(i2c_bus, ST_BUS_BUSY)

 

What we have been checking so far:

(1st)
To check if clocks are alright we read CCM Clock Gating Registers for I2C4 which all show a value of 0x3 which should be okay.

(2nd)
To check if there are any shortings, we did run probing on all 4 I2C buses while running linux.
The probing works with no errors for all 4 buses and the addresses of the connected peripherals will be detected.

(3rd)
We changed SPL to check which of the I2C buses seem to be accessable in general at this early stage.
We experience that only I2C1 does not throw errors on init.

(4th)
We temporary changed the connection of our PMIC to be connected to I2C1 instead of I2C4.
As expected, based on the results of (3rd), we have been able to successfully probe for the PMIC and tune voltages.

From our findings we assume there is something left to be done to enable other I2C busses than only the very first one while running in the SPL.
Does anybody have a hint what we may have missed so far ?

Thanks in advance.

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ralfgoebel
Contributor III

Hi David,

We had the same problem getting I2C4 running in SPL.

After a lot of debugging, I found out that the SION bit in the Pad Mux Registers was not set for I2C4. The bit is only active for I2C1:
https://source.codeaurora.org/external/imx/uboot-imx/tree/arch/arm/include/asm/arch-imx8m/imx8mm_pin...

I have fixed this by defining the I2c_pads_info structure as follows:

struct i2c_pads_info i2c_pad_info4 = {
	.scl = {
		.i2c_mode = IMX8MM_PAD_I2C4_SCL_I2C4_SCL | PC | ((iomux_v3_cfg_t)(IOMUX_CONFIG_SION) << MUX_MODE_SHIFT),
		.gpio_mode = IMX8MM_PAD_I2C4_SCL_GPIO5_IO20 | PC,
		.gp = IMX_GPIO_NR(5, 20),
	},
	.sda = {
		.i2c_mode = IMX8MM_PAD_I2C4_SDA_I2C4_SDA | PC | ((iomux_v3_cfg_t)(IOMUX_CONFIG_SION) << MUX_MODE_SHIFT),
		.gpio_mode = IMX8MM_PAD_I2C4_SDA_GPIO5_IO21 | PC,
		.gp = IMX_GPIO_NR(5, 21),
	},
};


Regards,
Ralf

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ralfgoebel
Contributor III

Hi David,

We had the same problem getting I2C4 running in SPL.

After a lot of debugging, I found out that the SION bit in the Pad Mux Registers was not set for I2C4. The bit is only active for I2C1:
https://source.codeaurora.org/external/imx/uboot-imx/tree/arch/arm/include/asm/arch-imx8m/imx8mm_pin...

I have fixed this by defining the I2c_pads_info structure as follows:

struct i2c_pads_info i2c_pad_info4 = {
	.scl = {
		.i2c_mode = IMX8MM_PAD_I2C4_SCL_I2C4_SCL | PC | ((iomux_v3_cfg_t)(IOMUX_CONFIG_SION) << MUX_MODE_SHIFT),
		.gpio_mode = IMX8MM_PAD_I2C4_SCL_GPIO5_IO20 | PC,
		.gp = IMX_GPIO_NR(5, 20),
	},
	.sda = {
		.i2c_mode = IMX8MM_PAD_I2C4_SDA_I2C4_SDA | PC | ((iomux_v3_cfg_t)(IOMUX_CONFIG_SION) << MUX_MODE_SHIFT),
		.gpio_mode = IMX8MM_PAD_I2C4_SDA_GPIO5_IO21 | PC,
		.gp = IMX_GPIO_NR(5, 21),
	},
};


Regards,
Ralf

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dzim
Contributor I

Hi Ralf,

to set the SION config bit exactly was the 'missing thing' and solves the problem for us as well.
Thank you very much for sharing your findings here !

Best Regards,

David
 

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dzim
Contributor I

Hi Igor,

thanks for your reply.
Unfortunately I don't think I get what you mean by 'tweaking i2c4'.

What we do right now is calling setup_i2c from board_init_f within spl.c for I2C4 (including the I2C pad infos for our board and the I2C4).
We do this right before we are trying to tune the PMIC voltages.

Would you please elaborate what additionally has to be done to use I2C4 for the PMIC connection (and thus tune the voltages before the init of the DRAM) ?

Regards,
David

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