In our custom board we have RGMII back to back connection between i.MX6Q and Zynq FPGA.
The Ethernet reference clocks (125Mhz) on both the processors are driven by different sources.
We have taken care of the driver changes to fake the presence of PHY and we have confirmed by probing all the signals.
During the signal analysis, we notice non-skewed tx_clk-tx_ctl and rx_clk-rx_ctl signals at imx6 end during the data transfer.
Both rx-clk and tx-clk are at 25Mhz (for 100M).
While connecting i.MX6 to the external PHY (instead of back to back RGMII) the skew settings on the PHY are mandatory for successful communication.
So, we feel that skewing would be required to get over this.
How can the skew be adjusted in case of the back-back connections? Does i.MX6 have internal skew settings which can be adjusted to meet our requirement?
Is there anything else we need to look at?
Unfortunately, the mx6 does not have any control over the skew of the tx_clk and rx_clk signals. This is typically done in the PHY so this control was left off of the mx6.
That being said, the easiest would be to add the skew capability into the FPGA and make the FPGA look like a PHY interface.
Also, since you have the FPGA and the mx6 sourced by 2 different reference sources, you will need to ensure synchronization of the clocks and the sampling. You will need to provide a FIFO or buffer inside the FPGA for the synchronization. I think it would simplify things if you had a common reference clock for both the mx6 and the FPGA but if you refer to the attached RGMII spec for signal timing and abide by the timing spec, you shouldn't have an issue there.
Please let me know how it goes.