Sorry if this is a duplicate. I realized that something has changed here and my old account didn't have email 'verified' and I couldn't find out how to send the 'verify email' - mail so I couldn't reply to the my own message.
First of all, I did check the old messages, but seemed that they were all something else than iMX6SX processor. Thus the question.
We have iMX6SX based product has has some problems passing EMC. We determined that slowing DDR from 400MHz to 316MHz would move the peaks enough that harmonics won't cause problem anymore.
Now the actual problem. I have excel sheet for iMX6SX that calculates the initialization values for DDR3. Problem with that is that the ddr clock is fixed at 400MHz and can't be changed. We had similar excel for iMX53 and there you could change the ddr clock too.
I did some digging from reference manual and find that from register CCM_CBCMR(0x020C 4018) you can select PFD2 by changing the PRE_PERIPH2_CLK_SEL field to 0b01. Then you can change the value in the CCM_ANALOG_PFD_528n(0x020C 8100) change the PFD2_FRAC from 0b011000 to 0b011100 (24 -> 30). I added both those writes to DCD in u-boot.
Well, the device didn't boot after that (I was bit suspecting that) so I assume that is not how you do it or I need to do something else.
Question is that how do I do that frequency change or is there updated version of that excel that supports ddr freq change as well?
Please use this Programming aid for your device https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX6SX-DDR3-Register-Programming-Aid/ta... in this one you can select the DDR clock frequency to bellow 400MHz but please consider the notes that come on the sheet, this could cause different behaviors than usual.
Hope this helps you.
I was bit hasty on accepting the solution. Seems this is not the case.
I used the updated excel sheet to calculate new values for mmdc - initialization and changed also the ddr clock to 316MHz from 400MHz. After going through all that the ddr clock still is 400MHz. I did see few register change when changing the ddr frequency, but seems that end result didn't.
File even has comment: setmem /32 0x020C4018 = 0x00260324 //DDR clk to 400MHz
That is exactly what I'm trying to change. PLL2_PDF2 is default to 400MHz and I want to change it to 316MHz. I know that I need also update the busclk - driver in Linux because it assumes that that frequency is 400MHz, but I think that was only when using low power modes.