Hello,
I managed to configure the ADMA2 of the iMX6S uSDHC module. I can read and write the SD card with it. However, the DMA interrupt is never set (DINT in uSDHC_INT_STATUS) while the Transfer COmplete bit is set.
Here is a dump of the registers after a successfull read operation:
=======================uSDHC0 dump===================
DS_ADDR: 0x1459be00
BLK_ATT: 0x00000200
CMD_ARG: 0x07400000
CMD_XFR_TYP: 0x123a0000
CMD_RSP0: 0x00000900
CMD_RSP1: 0xb9edb7ff
CMD_RSP2: 0x325b5983
CMD_RSP3: 0x00000b00
DATA_BUFF_ACC_PORT: 0x00000000
PRES_STATE: 0xff8d8088
PROT_CTRL: 0x00800222
SYS_CTRL: 0x008e013f
INT_STATUS: 0x00000003
INT_STATUS_EN: 0x157f513f
INT_SIGNAL_EN: 0x1070000a
AUTOCMD12_ERR_STATUS: 0x00000000
HOST_CTRL_CAP: 0x07f30000
WTMK_LVL: 0x08000880
MIX_CTRL: 0x00000037
FORCE_EVENT: 0x00000000
ADMA_ERR_STATUS: 0x00000000
ADMA_SYS_ADDR: 0x153dd008
DLL_CTRL: 0x00000000
DLL_STATUS: 0x00000200
CLK_TUNE_CTRL_STATUS: 0x00000000
VEND_SPEC: 0x20007809
MMC_BOOT: 0x00000000
VEND_SPEC2: 0x00000006
As you can see, the TC bit and the CC bit are set, but the DINT is not. However every IT bits are set in the STATUS_EN register.
Does someone know where I am going wrong?
Thank you i advance,
Regards,
Well, it is a proprietary RTOS so I am not allowed to share this fix (which shouldn't be meaningful for another OS).
Ok, got it.
I finally identified the problem of the ADMA setup: there was a bug in the cache management function --> the BD structure was not flushes correctly. I have also check the ERR004364 but it seems that there is not concerns with it (thank you anyway Yuri :smileyhappy:).
Which OS are you using? Care to share the fix?
Please try to apply the workaround for the next item from the Errata :
ERR004364 uSDHC: Limitations on uSDHC3 and uSDHC4 clock-gating
Workarounds:
uSDHC3 and uSDHC4 clock-gating controls should not be configured to gate the clocks in case
RAWNAND and APBADMA are used. There are two registers in CCM that need to be configured
accordingly:
• CCGR: Gating of the clock according to power mode
• CMEOR: Enable/Disable dynamic clock gating
http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
Have a great day,
Yuri
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