iMX6 Dual/Quad 4GB DDR3 on CS0

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iMX6 Dual/Quad 4GB DDR3 on CS0

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frodolai
Contributor IV

There are 4x H5TC8G63AMR on the iMX6 Dual board to have 4GB DDR3 on CS0. I tried to boot to Linux kernel 3.0.35_4.1.0 but it failed after "highmem bounce pool size: 64 pages". Below are the steps to recreate the test result.

 

1. Use Mx6DQSDL DDR3 Script Aid V0.09.xlsx and DDR Stress Tester 1.03 to get the memory init values (see attached).

2. Update flash_header.S and board .h file to get new U-boot

3. Update phys = memblock_alloc_base(imx6q_gpu_pdata.reserved_mem_size,   SZ_4K, SZ_2G); to get new kernel

4. Copy to SD card and boot.

 

Q1. Can CS0 support up to 4GB?

Q2. What's the PHYS_SDRAM_1_SIZE value? If I put 3840MB or above, boot process stops at Starting kernel... 2048MB~3839MB can only boot to "highmem bounce pool size: 64 pages"

Q3. What's the value to set in memblock_alloc_base()? I can boot to Ubuntu only when I set 2GB in uboot and SZ_2G in kernel board file.

 

Thanks.

Original Attachment has been moved to: AR6MXD_4GB.inc.txt.zip

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2 Replies

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Yuri
NXP Employee
NXP Employee

  The H5TC8G63AMR Datasheet states about two CS(s) [dual die package],
so the following parameters should be used for DRAM configuring, assuming
both are connected to i.MX6 :

// Manufacturer:  Hynix        

// Device Part Number: H5TC8G63AMR           

// Clock Freq.:     528MHz            

// Density per CS in Gb:       16            

// Chip Selects used:   2             

// Number of Banks:    8             

// Row address:          15            

// Column address:      10            

// Data bus width        64

Below is DRAM Datasheet link, which I used.

https://www.skhynix.com/inc/pdfDownload.jsp?path=/datasheet/pdf/dram/Computing_DDR3L_H5TC8G4(8_6)3AM...

Have a great day,
Yuri

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frodolai
Contributor IV

Hi Yuri,

I didn't notice the H5TC8G63AMR is a dual die chip. We need to change our hardware design to utilize the full 4GB memory. We'll stay with 2GB limitation now. Thanks.

Frodo