i.mx6Q/DL, is there a way to change PCIE TX pin drive strength?

[wallyyeh]

Hi, guys:

    Our boss just replace i.mx6Q with i.mx6DL for our product(using SDK_3.0.35-4.1.0), and it was almost a success. but we got some defect product which always hang up at PCIe initialization.

our HW team told me the signal on PCIe TX pin of the i.mx6DL is too high; and i.mx6Q seems have no this issue.

I just check the kernel source to see if there a way to change the resistance about the PCIe TX pin; but I can't find it,

I can only change all pins defined at kernel_3.0.35/arch/arm/plat-mxc/include/mach/iomux-mx6dl.h, and there seems no PCIe TX pin define here.

    Any suggestion would be help, thanks.

Wally

[wallyyeh]

OK, I search a lot of PCIe initialization hang up posts, lots people find out their power supply not stable.

My root cause of PCIe initialization hang up is the same, our design is attach PCIE_VP, PCIE_VPTX and VDD_SOC_CAP at the same place,

which made i.mx6 DualLite PCIE_VP reach voltage 1.2v, then make i.mx6 hang up when PCIe initialization. I need down the voltage to 1.12 to get pass the initialization.

since i.mx6 Quad have higher voltage limit for PCIe initialization(1.3v), that make sense that i.mx6Q doesn't have this issue.

[igorpadykov · Accepted solution]

Hi Wally

as this is not gpio cell, there are no drive strength/resistance, however

parameters of PCIe_PHY can be adjusted by changing the IOMUXC_GPR8 register

settings as described in app note PCIe Certification Guide for i.MX 6

http://cache.freescale.com/files/32bit/doc/app_note/AN4784.pdf

Best regards

igor

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[wallyyeh]

Dear igorpadykov:

    thanks for your help. :smileyhappy:  that's true that user need to look AN4784 for PCIe eye pattern.

I  change two register to pass the PCIe eye pattern:

1. 0x020E_0020 (IOMUXC_GPR8)

2. 0x01FF_C80C (PCIE_PL_G2CR)

[wallyyeh]

Hi, igorpadykov:

    our FAE also can't figure which value should change, and the description in i.mx6 DualLite/Solo reference manual is too poor to understand:

IOMUXC_GPR8 field descriptions

----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Field                                           |       Description

31–25                                         |      PCIe_PHY - This static value sets the launch amplitude of the transmitter when pipe0_tx_swing is set to  1'b0 (default state).

PCS_TX_                                    |

SWING_LOW                              |    

----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

0                                                   |    TBD

1                                                   |    TBD

all value description in GPR8 are "TBD", really can't figure out which value should we try, could you give me some directions or document?

[igorpadykov]

Hi Wally

unfortunately more descriptions are not available.

One can just formally follow AN4784

~igor

[wallyyeh]

Hi, igorpadykov:

    thanks for help :smileygrin: I just post your advice to my hardware co-worker, since I'm not familiar with IOMUXC_GPR8 register settings.

and my co-worker read this and mail our FAE for further detail, I'll reply this thread later after we done your advice.

Wally