i.MX8MM ECSPI maximum operational SCLK

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i.MX8MM ECSPI maximum operational SCLK

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Contributor III

Hi,

I am working with i.MX8MM EVK and 4.19-warrior yocto distribution.

From the i.MX8MM product datasheet:

"Full-duplex enhanced Synchronous Serial Interface, with data rate
up to 52 Mbit/s. Configurable to support Master/Slave modes, four
chip selects to support multiple peripherals"

The maximum SCLK can be 52MHz.

But, we have interfaced a slave to ECSPI2 and tried to do SPI transfer with 52MHz. it fails.

Could you please let me know up to what frequency(SCLK) SPI transfer is succesful in i.MX8MM EVK board?

Thank you, Sreedhar

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1 Solution
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NXP TechSupport
NXP TechSupport

Hello sreedhar_appala ,

>>The maximum SCLK can be 52MHz.

yes, right. On hardware, max clock is 52MHz.

>>Could you please let me know up to what frequency(SCLK) SPI transfer is succesful in i.MX8MM EVK board?

you can set speed to 30MHz.

>> Further advice for your test

in spi driver, ECSPI ROOT clock is limited 60MHz, and in eCSPI module, the clock is divided by 2 to be spi clock. so you can set max speed 30MHz.  But you can try higher speed by tuning spi driver like below:

diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index 91e32291c44e..00e092f2f4ff 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -1602,8 +1602,8 @@ spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
{
struct spi_imx_data *spi_imx = spi_master_get_devdata(master);

- clk_disable_unprepare(spi_imx->clk_ipg);
- clk_disable_unprepare(spi_imx->clk_per);
+ // clk_disable_unprepare(spi_imx->clk_ipg);
+ // clk_disable_unprepare(spi_imx->clk_per);
return 0;
}

@@ -1791,8 +1791,8 @@ static int spi_imx_probe(struct platform_device *pdev)

dev_info(&pdev->dev, "probed\n");

- clk_disable_unprepare(spi_imx->clk_ipg);
- clk_disable_unprepare(spi_imx->clk_per);
+ // clk_disable_unprepare(spi_imx->clk_ipg);
+ // clk_disable_unprepare(spi_imx->clk_per);
return ret

 

Try it , please!

[comment]

whatever it is successful or unsuccessful, 30MHz speed is recommended. because High speed will cause system to be unstable.

 

Have a nice day!

B.R,

Weidong

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2 Replies
63 Views
NXP TechSupport
NXP TechSupport

Hello sreedhar_appala ,

>>The maximum SCLK can be 52MHz.

yes, right. On hardware, max clock is 52MHz.

>>Could you please let me know up to what frequency(SCLK) SPI transfer is succesful in i.MX8MM EVK board?

you can set speed to 30MHz.

>> Further advice for your test

in spi driver, ECSPI ROOT clock is limited 60MHz, and in eCSPI module, the clock is divided by 2 to be spi clock. so you can set max speed 30MHz.  But you can try higher speed by tuning spi driver like below:

diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index 91e32291c44e..00e092f2f4ff 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -1602,8 +1602,8 @@ spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
{
struct spi_imx_data *spi_imx = spi_master_get_devdata(master);

- clk_disable_unprepare(spi_imx->clk_ipg);
- clk_disable_unprepare(spi_imx->clk_per);
+ // clk_disable_unprepare(spi_imx->clk_ipg);
+ // clk_disable_unprepare(spi_imx->clk_per);
return 0;
}

@@ -1791,8 +1791,8 @@ static int spi_imx_probe(struct platform_device *pdev)

dev_info(&pdev->dev, "probed\n");

- clk_disable_unprepare(spi_imx->clk_ipg);
- clk_disable_unprepare(spi_imx->clk_per);
+ // clk_disable_unprepare(spi_imx->clk_ipg);
+ // clk_disable_unprepare(spi_imx->clk_per);
return ret

 

Try it , please!

[comment]

whatever it is successful or unsuccessful, 30MHz speed is recommended. because High speed will cause system to be unstable.

 

Have a nice day!

B.R,

Weidong

View solution in original post

58 Views
Contributor III

Hi Weidong,

Thank you very much for the complete details.

I will try to tune the SPI clock as per your suggestion.

Thank you once again.

Regards, Sreedhar

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