Usage of Signal M4_NMI / M7_NMI

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Usage of Signal M4_NMI / M7_NMI

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Contributor III

i.MX8MQ / i.MX8MM / i.MX8MN has the opportunity tho mux this signal on PAD GPIO1_IO05. In the reference manual ist only a link to CortexM Documentation from ARM

In the implementatation of above called SOC: is this signal an input to trigger the NMI exception our an Output signalling the occurence of the exception? What is the active level of the signal - Low or High?

Thanks in Advance

Markus

 

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NXP TechSupport
NXP TechSupport

Hi Markus

 

it is input to trigger the NMI exception, active level high.

 

Best regards
igor

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NXP TechSupport
NXP TechSupport

Hi Markus

 

it is input to trigger the NMI exception, active level high.

 

Best regards
igor

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