i.MX8MQ / i.MX8MM / i.MX8MN has the opportunity tho mux this signal on PAD GPIO1_IO05. In the reference manual ist only a link to CortexM Documentation from ARM
In the implementatation of above called SOC: is this signal an input to trigger the NMI exception our an Output signalling the occurence of the exception? What is the active level of the signal - Low or High?
Thanks in Advance
Solved! Go to Solution.