i.MX8M Mini PCIe PHY clock generation - Setting in CMN_REG063 register

[OliW]

I have a custom hardware running i.MX8M Mini with Android 13 2.2.0, using kernel 6.1.

There is an Intel ethernet NIC connected to the PCIe interface of the i.MX8M.

Now I have the problem, that the PCIe link does not come up when driver is loaded or the link sometimes interrupts while the system is running.

Analysing the problem showed, that kernel 6.1 now has a separate driver for the i.MX8M PCIe PHY. This driver configures the CMN_REG063 of the PCIe PHY to I_PLL_REFCLK_FROM_SYSPLL when the clock pins are configured to be output. The driver in older 5.15 kernels did not touch this register at all, so leaving it at reset value which is AUX_IN.

Measuring the clock signal on the boards shows, that using SYSPLL clock is only around 90MHz and the signal has some jitter. Using AUX_IN produces a clean clock around 100MHz as expected.

Removing the write access to CMN_REG063 (use AUX_IN) seems to solve my problems regarding the PCIe link to the ethernet NIC.

Now my questions:

- Can someone give me some more details about the meaning of the CMN_REG063? Which PLL is used for each setting?

- Is there any reason why the new PHY driver sets this register to use SYSPLL?

- May there be some misconfiguration regarding SYSPLL because it does not produce a clean clock signal?

[Lylwa]

Hi,

Regarding CMN_REG063, you can consult the Reference Manual:

0X: AUX_IN (PLL clock) 10: I_PLL_REFCLK_FROM_IO 11: I_PLL_REFCLK_FROM_SYSPLL

I haven't observed any recent modifications to the driver, so I can't provide insights on such changes.

Thus far, we haven't encountered any issues on our EVK.

Best regards, Wink

[AldoG]

Hello,

For CMN_REG063 you may refer to the Reference Manual:

• 0X: AUX_IN (PLL clock)
• 10: I_PLL_REFCLK_FROM_IO
• 11: I_PLL_REFCLK_FROM_SYSPLL
  
  

I cannot see any recent changes to the driver so I cannot comment of such change.

We haven't received any issues on our EVK so far,

Best regards,
Aldo.

[OliW]

Hi AldoG,

the change to the driver came because of the switch from kernel 5.15 to kernel 6.1. In 5.15 the PHY setup was done in driver directly "file pci-imx6.c, function imx6_pcie_init_phy). The the register CMN_REG63 is never touched when the driver is configured to not use internal **bleep** source (ext_osc=0 in device tree).

In kernel 6.1 init of PCIe PHY has moved to phy-fsl-imx8m-pcie.c. There in function "imx8_pcie_phy_power_on" the pin direction is evaluated. When IMX8_PCIE_REFCLK_PAD_OUTPUT is configured in device tree, then the CMN_REG63 is written with the fixed value of 0xC0 (bit 7 and bit 6 set).

On EVK there is an external clock generator attached to the PCIe interface. So this piece if code is never touched in EVK. The clock pins are configured as IMX8_PCIE_REFCLK_PAD_INPUT.

Our custom hardware does not have an external clock generator for PCIe but uses the iMX8M to output the PCIe reference clock.

Do you know about any issues/errata when using the i.MX8M Mini as clock generator for PCIe reference clock?

What is the difference between AUX_IN and I_PLL_REFCLK_FROM_SYSPLL setting?

[AldoG]

Hello,

Sorry for the delay, it was difficult to find the actual commit for such changes, I think that this is the one:
https://patchwork.kernel.org/project/linux-phy/cover/1637028976-9201-1-git-send-email-hongxing.zhu@n...

For AUX_IN difference from  SYS_PLL, please note that both have different clock frequencies, as it is defined in device tree:
https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi#L59...

Saludos,
Aldo.

[OliW]

Hi Aldo,

AUX_IN selects the PCIE1_AUX clock which is set to 100 MHz in device tree. Clear now.

But what clock used when SYS_PLL is selected? PCIE1_CTRL is 250MHz.So I think it is not that clock.

PCIe phy has s separate clock defined in device tree (IMX8MM_CLK_PCIE1_PHY):

https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/arch/arm64/boot/dts/freescale/imx8mm.dtsi#L1333

It is set to 100MHz and derived from PLL2_100MHz as parent. Is it this clock? Than I am wondering why it produces instabilities an PCIe because it should also be an accurate 100MHz clock.

Regards

Oliver

[mb1]

Hi.

We did some measurements with mickledore BSP and 6.1 Kernel.
What we found is:
- non-stable frequency of 100 MHz PCIe clock when taken from processor
- Jittering clock
- Wrong duty cycle, around 70:30 ratio

We experimented with the registers from pcie phy and now get a clean 100 MHz clock with duty-cycle 50:50 from processor without external oscillator. In my opinion there's still something wrong how the devicetree setting for reclk-pad-mode is handled.

Find the "quick and dirty" solution patch for the pcie phy kernel driver attached. It just does not touch/zeros the 

AUX_PLL_REFCLK_SEL
field inside

CMN_REG063

register.

See ref. manual: 11.4.3.1.101.3

Maybe this is useful to someone else.

[Aschwin]

Hi, 

we seem to have a similar problem. Did you receive any conclusive answers elswhere?

Regards,

Aschwin