i.MX8M: CSI Bridge EOF Interrupt generation

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i.MX8M: CSI Bridge EOF Interrupt generation

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gianfranco
Contributor II

Hi Everyone,

I have a custom board based on i.MX8M processor. I have a question on CSI Bridge End Of Frame interrupt generation. On the reference manual (Chapter 13.4.2.4.2) it is written as follows:

"An EOF interrupt is generated when the frame ends and the complete frame data in
RXFIFO is read.
The EOF event triggering works with the RX count register (CSIRXCNT). Software sets
the RX count register to the frame size (in words). The CSI RX logic then counts the
number of pixel data being received and compares it with the RX count. If the preset
value is reached, an EOF interrupt is generated and the data in the RXFIFO are read. If a
SOF event is detected before this happens, the EOF interrupt is not generated. "

Anyway in the driver source mx6_capture.c I don't see the logic described above. I do see the rxcnt member of the csi_dev object and the definition of the RXCNT register but I cannot find the piece of software where the RXCNT register gets updated with the number of words corresponding to the frame size.

I have a problem with that EOF is not generated only for certain value of acquisition ROIs. So I wanted to debug the piece of software where EOF is generated and RXCNT gets updated. 

Could you point out where this logic is happening?

 

Thanks,

Gianfranco

 

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gianfranco
Contributor II

Dumping the registers I realized that I had a wrong hs-settle configuration to the MIPI Tx. Once fixed this I can successfully acquire image.

So we can resolve this post.

Anyway, it is not yet clear to me the RXCNT register updates. Can you explain or just point me out the piece of sw where the logic of the reference manual is implemented?

Thanks for your help,

GIanfranco

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521 Views
gianfranco
Contributor II

Dumping the registers I realized that I had a wrong hs-settle configuration to the MIPI Tx. Once fixed this I can successfully acquire image.

So we can resolve this post.

Anyway, it is not yet clear to me the RXCNT register updates. Can you explain or just point me out the piece of sw where the logic of the reference manual is implemented?

Thanks for your help,

GIanfranco

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joanxie
NXP TechSupport
NXP TechSupport

pls refer to the 13.7.6.6 CSI RX Count Register (CSI_CSIRXCNT), Whenever the RX FIFO is being read, by either the CPU or the embedded DMA controller, the counter value is updated and compared with this register. If the values match, then an EOF interrupt is triggered

so you can enable EOF bit, then dump the registers to check this, you also can read CSIRXCN register, you should find the relationship between them

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joanxie
NXP TechSupport
NXP TechSupport

could you dump the CSI registers here?

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