Hi,
I Try to use the eDMA engine for DRR to DDR transfer w/ some transformation from Cortex-M7 domain on a i.MX8MP SoC. The Cortex A53 OS is Android AOSP (NXP released) 11.0.0-2.6.0, the Audio control block is **not** used from Cortex A53 domain.
On Cortex M7 (w/ custom bare metal firmware), clock domains are claimed and power domain is requested up from CM7. There is no RDC or CSU configuration yet. CM7 domain can access all eDMA engine registers (except MP_INT register which will trapped mcu on read access...). audio ahb root clock is configured at full speed (400MHz) and eDMA clock is enabled in audio mix, DSP is hold in stall state.
The issue we've got is that the DDR to DDR throughput seems to be very low, about 20MiB per seconds, direct access from cpu is ten times faster.
So my questions is, Is this the normal throughput for eDMA engine ? Do I need NoC QoS special configuration for my needs ? Am I missing an obvious configuration bloc ?
Thank in advance.
