i.MX7D - Is NVCC_DRAM switch necessary?

[billgessaman]

I have LPSR mode working on our custom board with DDR3L memory that is based on the i.MX7D Sabre design, but it does not include a load switch to turn off NVCC_DRAM when in LPSR mode by using the SNVS_TAMPER9 pin to control the load switch.  Measured power consumption when in LPSR is approximately 25mW which is acceptable for our use case, but what I would like to know is whether keeping NVCC_DRAM (and DRAM_VREF) powered in LPSR may damage the i.MX7D?

Thanks,

Bill Gessaman

[gusarambula]

Hello Bill Gessaman,

I would strongly advice against maintaining the NVCC_DRAM supply during LPDR mode as this is not the intended usage and it may cause harm to the processor.

My apologies for the inconvenience.

Regards,