[i.MX6UL] USDHC1 CLOCK Voltage issue with AW-CM276NF WIFI card

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[i.MX6UL] USDHC1 CLOCK Voltage issue with AW-CM276NF WIFI card

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john2207
Contributor I

Hi ,

We are having i.MX6UL soc based custom board and AW-CM276NF WIFI card connected to usdhc1 (mmc@2190000). Currently, Interface is up but ping test get failed (Destination Host unreachable) after sometime (~17 sec). We checked mmc0 clock frequency (/sys/kernel/debug/mmc0/clock) which is 198MHz and USDHC1_CLK voltage is 1.2V and CMD/DATA lines voltage is 1.8V.

We tried by reducing to 100 Mhz and checked ping test (more that 10 hours). It runs well without any issues. Also, USDHC1_CLK voltage is 1.8V. Since WIFI bandwidth will be limited for 100 MHz, we can't use.

We suspected that clock voltage causing issue and tried to improve USDHC1_CLK pad drive strength (DSE) with below options but didn't get succeeds.

011 - DSE_3_R0_3 — R0/3
101 - DSE_5_R0_5 — R0/5
110 - DSE_6_R0_6 — R0/6
111 - DSE_7_R0_7 — R0/7

Please find the kernel device tree settings as below,

&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <4>;
keep-power-in-suspend;
status = "okay";
};

pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
>;
};

pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9

>;
};

pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9

>;
};


Please help us to solve this issue.

 

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john2207
Contributor I

Hi @igorpadykov ,

Thanks for your reply. Latest update in our previous observations,

previously, we have measured the CLOCK voltage at Host (CPU) side and found 1.2V. But when we measured at device side (WIFI). We found it is 1.8V. It seems like some signal reflection because of high frequency. Now, we can eliminate clock voltage issue.

Please advise your thoughts.

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igorpadykov
NXP Employee
NXP Employee

Hi Janarthanam

 

such issue may be caused by capacitance of USDHC1 CLOCK line (probably due to

long cable) and signal loss at higher frequencies. It can be estimated using formula

in Table 14. Maximum Supply Currents   i.MX 6UltraLite Applications Processors for Consumer Products Data Sheet

 

1.jpg

Best regards
igor

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