Hi community,
Our partner have a question about i.MX6SDL IPU SRM entries.
Please see Table 38-37 in IMX6SDRM Rev.1.
Our partner tried to access to IPU_DP_COM_CONF_SYNC (addr : 0x1F40000), but it was illegal access.
Then, 0x140000 seems the correct address, is this correct?
Best Regards,
Satoshi Shimoda
解決済! 解決策の投稿を見る。
Hello Satoshi San,
IPU supports frame by frame task switching. This means that a sub-block can handle a frame with one configuration and handle the following frame with different
configuration. Changing the configuration is done by updating the sub-block's parameters. In order to allow automatic flow without a need of the SW to update all the parameters at the frame boundaries. A Register of a sub-block that has the shadowing capabilities has a shadow register file that resides in the Shadow Register Memory.
So the DP sub-block, SRM_MODE can be 00, 10 or 11. If the SW set to 11: after the update the state machine is automatically moved to 10 mode. So you are not finding the 1F40000, instead you got the 140000.
Hope this clarifies.
Have a great day,
Jaime
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Hello Satoshi San,
IPU supports frame by frame task switching. This means that a sub-block can handle a frame with one configuration and handle the following frame with different
configuration. Changing the configuration is done by updating the sub-block's parameters. In order to allow automatic flow without a need of the SW to update all the parameters at the frame boundaries. A Register of a sub-block that has the shadowing capabilities has a shadow register file that resides in the Shadow Register Memory.
So the DP sub-block, SRM_MODE can be 00, 10 or 11. If the SW set to 11: after the update the state machine is automatically moved to 10 mode. So you are not finding the 1F40000, instead you got the 140000.
Hope this clarifies.
Have a great day,
Jaime
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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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