i.MX6SDL GPIOx_PSR register value.

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i.MX6SDL GPIOx_PSR register value.

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satoshishimoda
Senior Contributor I

Hi community,

Our partner have a question about i.MX6SDL GPIO.

Please see chapter 29.5.2 in IMX6SDLRM Rev.1.

It says "If GDIR[n] is cleared and IOMUXC input mode is not GPIO, then reading DR[n] always returns zero".

With same condition (GDIR[n] is cleared and IOMUXC input mode is not GPIO), how about the value of GPIOx_PSR register?

Does is return zero same as GPIOxDR register?

Best Regards,

Satoshi Shimoda

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Yuri
NXP Employee
NXP Employee

The PSR register reflects state of pin in (GPIO) input mode.

(case B)

~Yuri.

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881件の閲覧回数
Yuri
NXP Employee
NXP Employee

   GPIOx_PSR register(s) is intended to read actual state of internal

signals, as it is configured by IOMUXC.  Please look at  Figure 29-1

(Chip IOMUX Scheme) of the IMX6SDLRM.


Have a great day,
Yuri

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satoshishimoda
Senior Contributor I

Hi Yuri,

Thank you for your reply.

> as it is configured by IOMUXC. 

Sorry, I did not understand well the meaning of the above your comment.

Which is correct?

A. GPIOx_PSR can get actual pad state even if IOMUX is not set to GPIO.

B. GPIOx_PSR can get actual pad state only when IOMUX is set to GPIO.

Best Regards,

Satoshi Shimoda

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Yuri
NXP Employee
NXP Employee

The PSR register reflects state of pin in (GPIO) input mode.

(case B)

~Yuri.

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satoshishimoda
Senior Contributor I

According to your reply, GPIOx_PSR does not return the actual pad state when IOMUX is not set to GPIO.

Then, what value is returned when read GPIOx_PSR in the case?

Zero? Indeterminate value? or keep actual pad state if the out of reset condition is "GPIOx_IOxx/Input/PU(100K)" of the pad?

Best Regards,

Satoshi Shimoda

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Yuri
NXP Employee
NXP Employee

"The IOMUX must be configured to GPIO mode for PSR to reflect the state
of the corresponding signal. Otherwise the register shows the default values

as set by the IOMUX."

~Yuri.

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