i.MX6Q and PF0100

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i.MX6Q and PF0100

Contributor III

Dear community.

Our customer has question below.

Problems are occurring with combination of i.MX 6Q and PF 0100.

In the Schematic checking page of the HW Design Checking List, there is the following statement in the line 18 of "Power and Decouple".
PF0100 default configuration power up sequence can not meet i.MX6 requirement. When using default configuration, please add an external reset IC. SABRE AI reference design can be a reference.

Which specifications do not match? Is it necessary to connect the reset IC externally with the combination of i.MX6 and PF0100?

What is the correct answer to restart  the reset in milliseconds after PORB VDD_ARM_CAP starts up?




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NXP TechSupport
NXP TechSupport

I cannot find the statement you've mentioned in the official Hardware Design Guidelines document by NXP. Most likely, you use some other unofficial document, that NXP cannot be responsible for. Moreover, the statement looks confusing for me, since the MMPF0100 PMIC has been especially designed to be PM companion IC for i.MX6 series processors and it definitely meets all the requirements. No additional external components are required.

Have a great day,

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