i.MX6 CPU cache.

[satoshishimoda]

Hi community,

I have some questions about i.MX6S CPU cache.

Please see the questions as following.

[Q1]

Actually, i.MX6S cache is changed from invalid to valid when memory access by USB or Ethernet.

It is not expected behavior, so our partner want to find a solution to avoid this issue.

Then, could you let me know the condition to change the cache invalid -> valid?

[Q2]

Could you let me know the condition to accommodate the cache and memory when cache data and memory data is different?

Is there a possibility to satisfy the condition when a peripheral accesses to memory?

Best Regards,

Satoshi Shimoda

[igorpadykov]

Hi Satoshi,

please look at link below and SDK example armv7_cache.c

https://community.freescale.com/thread/315745

i.MX 6Series Platform SDK : Bare-metal SDK

Caches operation is well described in ARM (www.arm.com)

document DDI0388H_cortex_a9_r4p0_trm.pdf

Best regards

chip

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------