Hi all,
I'm working on a custom i.MX51 babbage board.
When I migrated from kernel 2.6.35 to freescale git branch imx_2.6.38_11.11.01 (and also imx_2.6.38_11.09.01 and imx_2.6.38) we noticed that the six low significative bit of blue color (from DISP1_D0 to DISP1_D5) was no more active.
The effect is that blu have a "gross" definition; red and green are ok: 8 bit color depth each oen.
If we rollback to 2-6-35 all return pk.
We sow the same behavior on an original Freescale i.MX51 Babbage. Does anyone notice this problem too ? Any idea to solve ?
We are using video default configuration, (we also try other but nothing changed: kernel 2.6.35 works, 2.6.38 doesn't)
.interface_pix_fmt = IPU_PIX_FMT_RGB24,
.mode_str = "1024x768M-16@60",
.default_bpp = 16,
we tested both dvi and LVDS output.
Hope someone can help me, just to say if his or her babbage board wors ok with 2.6.38
Bye
Giuseppe
I solved. Write here the solution for future reference.
In this moment on Freescale GIT repository they miss this piece of code from file:
"arch/arm/mach-mx5/cpu.c":
#include <linux/clk.h>
#include <linux/err.h>
........................
static void __init ipu_mipi_setup(void)
{
struct clk *hsc_clk;
void __iomem *hsc_addr;
hsc_addr = MX51_IO_ADDRESS(MX51_MIPI_HSC_BASE_ADDR);
hsc_clk = clk_get_sys(NULL, "mipi_hsp");
if (IS_ERR(hsc_clk)) {
pr_err("failed to get mipi clock\n");
return;
}
clk_enable(hsc_clk);
/* setup MIPI module to legacy mode */
__raw_writel(0xf00, hsc_addr);
/* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */
__raw_writel(__raw_readl(hsc_addr + 0x800) | 0x30ff,
hsc_addr + 0x800);
clk_disable(hsc_clk);
clk_put(hsc_clk);
}
static int __init post_cpu_init(void)
{
unsigned int reg;
void __iomem *base;
if (cpu_is_mx51())
ipu_mipi_setup();
..................
Bye
Giuseppe