i.MX257: Drive GPIO output low in Keeper enabled

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i.MX257: Drive GPIO output low in Keeper enabled

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norishinozaki
Contributor V

Hello Champs,

A GPIO is connected to a FPGA and the GPIO set to Output High when running.

When S/W reset, they would like to drive the GPIO Low in order to reset the FPGA.

However the GPIO wouldn't go Low when reset.

They pulldown the pad externally in 10K resistor and set Keeper enabled during reset to IOMUX setting done.

(Keeper is disabled on normal operation).

Their question is,

With internal Keeper enabled, how much current should I give in order to driver the pin low?

I don't understand the question well but I think internal Keeper load doesn't effect on the current to drive the pin.

However from AN5078 "Influence of Pin Setting.." document describes Keeper has Typ 130K load.

pastedImage_3.png

From i.MX25 datasheet, Iol is 2.0mA for slow mode and Standard Drive GPIO pins.

So in order to drive the pin Low, minimum 2.0mA can be input to i.MX25.

pastedImage_2.png

Regardless the load of external pullup/down resistors and FPGA loads, how much current they should give in order to drive the pin output low?

BR,

N.Shinozaki

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art
NXP Employee
NXP Employee

Unfortunately, I don't understand the question exactly. When the pin is configured as GPIO input with keeper disabled (default state of most pins out of reset), it behaves as hi-Z, so, any pulldown resistor (even 1MOhm) can keep it Low. When the pin is configured as GPIO input with keeper enabled, it behaves as equivalent resistance of typ. 130kOhm as you listed, connected to the current state level. In this case, 10kOhm pulldown should be enoug to always pull the pin over to Low state. If the pin is configured as GPIO output, trying to drive it externally to pull it over to another state is not a good pratice that can lead to permanent GPIO driver damage.


Have a great day,
Artur

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norishinozaki
Contributor V

Hello Artur,

Without considering Keeper impedance, do I just need to refer to IoL in the table 20?

For example, in "slow mode" and "Standard Drive", the GPIO can pull in Min. 2.0mA for VoL.

If we drive 2.1mA, the pin goes above VoL?

BR,

N.S

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art
NXP Employee
NXP Employee

Dear Nori Shinozaki,

Sorry for the delay, I was on the vacation.

Q. Without considering Keeper impedance, do I just need to refer to IoL in the table 20?

A. Yes, you are right.

Q. For example, in "slow mode" and "Standard Drive", the GPIO can pull in Min. 2.0mA for VoL.

If we drive 2.1mA, the pin goes above VoL?

A. Typically no, but it is not guaranteed to drive more than 2.0mA for these conditions.

Best Regards,

Artur

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norishinozaki
Contributor V

Hello Artur,

Thanks for comment.

>If the pin is configured as GPIO output, trying to drive it externally to pull it over to another state is not a good practice that can lead to permanent GPIO driver damage.

Please consider a case in which i.MX25 GPIO resets a FPGA.

When SW reset, i.MX25 GPIO needs to pull it down to produce active-low signal in order to reset the FPGA.

Isn't this recommended?

They have this design working with Renesus SoC.

BR,

Nori Shinozaki

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