i.MX 8M Plus Quad (MIMX8ML8CVNKZAB) How do you connect 1588/TSN/SyncE to an external PHY?

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

i.MX 8M Plus Quad (MIMX8ML8CVNKZAB) How do you connect 1588/TSN/SyncE to an external PHY?

693 Views
Dan1111
Contributor III

How do you connect ENET_QOS_1588 / TSN / Synchronous Ethernet to an external PHY?

I already have RGMII connected but don't know what to do with the 1588 pins, and 1588 is a feature we'd like to implement.

0 Kudos
Reply
6 Replies

417 Views
Dan1111
Contributor III

Sorry about the spam. To add to my questions, what does it mean to have event0_in (or event0_aux_in) and event0_out on separate pins? Since both are labelled event0, does that mean only 1 of these signals can be used? Or that they are tied together somehow?

0 Kudos
Reply

537 Views
Dan1111
Contributor III

I tried to edit my last comment to add these notes, but I ran out of time to edit the post.

  • I'm not sure how cascading PHYs changes the way I would connect these event signals.
  • The Primary PHY has 4 GPIO that can be set to input or output.
  • The Secondary PHY has 6 GPIO that can be set to input or output, because it doesn't need to lose 2 for the cascaded MDC and MDIO pins.
0 Kudos
Reply

537 Views
Dan1111
Contributor III

Thanks Zhiming,

 

Sorry, I'm still confused by the schematic architecture.

Does my block diagram below represent what I need to do?

We need to support PTP and TSN, just not necessarily at the same time. So I'm trying to make the hardware flexible so that the software team have the connections they need for either solution.

Dan1111_1-1722927416736.png

 

Kind regards,
Dan

0 Kudos
Reply

645 Views
Dan1111
Contributor III

Thanks Zhiming_Liu,

 

I don't think my PHY has enough pins for that, which is where I'm confused. It only has 4 GPIO that can be assigned to 1588/TSN/SyncE.

Do we need to connect both IN and AUX_IN for each event? Or just Out and either IN or AUX_IN?

Each of the PHY's GPIO has the following configuration options. Is it P2P_E* or the SyncE options I need for 1588 ?

  • 0x0 = GPIO[12]
  • 0x1 = Defaults to PTP_TRIG – Precise Timing Protocol Trigger Generate
  • Output - is selectable per TCAM Time Sel (PTP Global offset 0x1E)
  • 0x2 = PTP_EVREQ – Precise Timing Protocol Event Request Input
  • 0x3 = PTP_EXTCLK – Precise Timing Protocol External Clock Input
  • 0x4 = RX_CLK0 – SyncE Receive Clock 0 Output
  • 0x5 = RX_CLK1 – SyncE Receive Clock 1 Output
  • 0x6 = PTP_1PPS – Precise Timing Protocol 1 Pulse Per Second
  • 0x7 = Reserved for future use

 

Kind regards,

Dan

0 Kudos
Reply

623 Views
Zhiming_Liu
NXP TechSupport
NXP TechSupport

Hi @Dan1111 

There are two general applications of IEEE1588. 

1.To synchronize the CPU and IO cards, you can use the MAC to MAC RGMII connection for 1588 PTP synchronization. NXP has supported IEEE1588 PTP function in BSP.

2.For periodic events from the CPU card to the IO card, you can use one of the 1588_EVENTx_OUT signals. For this case, you need connect one or two 1588_EVENT signals between PHY and SOC, this is decided by your application. You don't have to connect all of these signals in RM.



Best Regards
Zhiming

0 Kudos
Reply

649 Views
Zhiming_Liu
NXP TechSupport
NXP TechSupport

Hi

You need connect event gpios between i.MX and external PHY  to sync events.

Zhiming_Liu_0-1721614093516.png

Then set pinctrl function in devicetree, for example, add pinctrl node using 

MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT and 
MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN



Best Regards
Zhiming

0 Kudos
Reply