I am working on a custom design based on the i.MX 8M Plus (Quad) processor. We are using the MIMX8ML8CVNKZAB processor for design. I ran into failures using the mscale_ddr_tool _v3.30 when trying to test my board from -25C to +85C, the rated temperature of the LPDDR4, MT53E1536M32D4DT-046 WT:A. I was seeing failures at both temperature extremes and have solutions for each, but I am wondering if the software can be updated to help with them.
-25C : I found that the default boot software is running the ARM core at 1800Mhz, which is higher than the I-Temp version of the processor is rated for (1600MHz). I changed the "Clock" setting in the DDR Tool GUI to 1600Mhz, but the output was still showing 1800MHz for the ARM clock. A setting of 1200MHz for the "Clock" did work in the output, and my LPDDR4 Stress Test passes at -25C with this setting. Is it possible to update the software to support the I-Temp version of the processor and the max speed of 1600MHz on the ARM core? Since the RAM is still operating at 2000MHz I am pretty confident in our system design, but it would be nice to run everything at full speed.
+85C : I was seeing failures on the RAM when the ambient temperature reached about +75-80C. I was able to get the boards to pass by manually turning off the DERATE_ENABLE and setting the T_RFC_NOM_X32 to half the value the RAM chip says for room temperature operation. A similar scheme was utilized for the Mini/Nano version of the processor to work around a silicon bug (ERR050805). However, it is not clear to me why I need to make this adjustment for the Plus processor; I was expecting that the DERATE_ENABLE should be working for the Plus. Can you tell me what the RAM controller/code does if the RAM chip MR4[2:0] (Refresh Rate) reports back 3b111: SDRAM High temperature operating limit exceeded? I would think it keeps operating at 0.25x refresh, with de-rating, but I wanted to verify. Related, I noticed the RPA spreadsheet sets DERATE_MR4_TUF_DIS to 1 to disable the Temperature update flag from the LPDDR4 chip; I assume that means the software/controller checks the Refresh Rate on a regular basis instead of using an interrupt?
Thanks
You can use the following command to see the supported CPU frequency:
cat /sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state
And you also need to confirm your source code setting, if support all the frequency.
Thanks for the response. The LPDDR4 DDR Tool boots from USB and the boot code is a pre-configured binary from NXP, so I do not have access to look at the source code or update it for the necessary frequencies. I was hoping NXP has a planned update to the tool to support the I-Temp 8M Plus processor.
All our tool are here by now https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/110...