i.MX 6SX SABRE Board DDR3 Layout SI/Timing analysis

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i.MX 6SX SABRE Board DDR3 Layout SI/Timing analysis

Contributor I

We are designing a board with a IMX6 SoloX, this board is partially based upon the I.MX 6SX sabre board. We are also using 2 4Gb DDR3L chips. My PCB stack-up is a bit different compared to the sabre board but 50 ohm SE en differential pair widths etc are quite similar. I could copy the DDR3 layout from the sabre board and make slight adjustments to match the widths and lengths of the vias etc. 

But the sabre board has the Adress and command group partially routed on outer layers and the other signals via an inner layer. As far as I can measure the signals that travel via the inner layer are length matched to the traces that run via the outer layers. But has been accounted for the propogation delay difference between inner and outer layers and the extra vias? 

Or has SI and timing analysis been done on the Sabre design and proved it would not be needed?

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NXP TechSupport
NXP TechSupport

Hello Thomas Stegmeijer,

Recommendations on the i.MX6SX Hardware Design Guide do not consider the effect on vias but following these recommendations should be enough for robust operation even with the added effect of vias (which are virtually unavoidable considering the processor’s package). As you pointed out vias do add some propagation delays but most often lines inside a byte group are close to one another and use the same amount of vias so these delays do shouldn’t miss match the signals too much.

The SABRE board itself does not completely comply with all the recommendations on the HW Design Guide, but it was tested using the DDR Stress Toool and successfully calibrated.

The great advantage of the i.MX6 external memory controller is that it’s very flexible and allow to compensate for certain length differences (and it helps that the DDR3 works in more manageable speeds than for example DDR4). The SABRE design is robust enough and has been tested but it can certainly be improved.

I hope this helps!

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